Change in coreboot[master]: nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36055 )
Change subject: nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup ......................................................................
nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup
During the raminit the CPU gets reset but the platform does not. To deal with TPM init failure (a TPM can only be started up once) ignore the invalid POSTINIT return code.
Change-Id: Ib15e796914d3e6d5f01b35fa46b3ead40f56122b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/nehalem/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36055/1
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index a88d4c9..7b56841 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -29,6 +29,8 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE + # CPU is reset without platform/TPM during romstage + select TPM_STARTUP_IGNORE_POSTINIT
config MMCONF_BUS_NUMBER int
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36055 )
Change subject: nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup ......................................................................
Patch Set 2:
Tested how?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36055 )
Change subject: nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36055 )
Change subject: nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup ......................................................................
nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup
During the raminit the CPU gets reset but the platform does not. To deal with TPM init failure (a TPM can only be started up once) ignore the invalid POSTINIT return code.
Change-Id: Ib15e796914d3e6d5f01b35fa46b3ead40f56122b Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36055 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/nehalem/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index a88d4c9..7b56841 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -29,6 +29,8 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE + # CPU is reset without platform/TPM during romstage + select TPM_STARTUP_IGNORE_POSTINIT
config MMCONF_BUS_NUMBER int
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36055 )
Change subject: nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36055/3/src/northbridge/intel/nehal... File src/northbridge/intel/nehalem/Kconfig:
https://review.coreboot.org/c/coreboot/+/36055/3/src/northbridge/intel/nehal... PS3, Line 32: # CPU is reset without platform/TPM during romstage come to think of it: is that really a property of the northbridge and not of the specific board?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36055 )
Change subject: nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36055/3/src/northbridge/intel/nehal... File src/northbridge/intel/nehalem/Kconfig:
https://review.coreboot.org/c/coreboot/+/36055/3/src/northbridge/intel/nehal... PS3, Line 32: # CPU is reset without platform/TPM during romstage
come to think of it: is that really a property of the northbridge and not of the specific board?
The reset is issued in the northbridge code, but is a bit hidden: "MCHBAR32_OR(0x1af0, 0x10);" right before halt() on line 4260 does that.
-
Arthur Heymans (Code Review) -
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)