Change in coreboot[master]: mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants

[Cliff Huang (Code Review)]

Attention is currently required from: Cliff Huang.
Hello Cliff Huang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/62744

to review the following change.

Change subject: mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants
......................................................................

mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants

This sets EPP value to be 45% for all Adl RVP variants.

Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.

TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.

Signed-off-by: Cliff Huang 
Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/adlrvp/devicetree_n.cb
3 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/62744/1

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 9bd99b1..bc1cf8f 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -168,6 +168,10 @@

register "CnviBtAudioOffload" = "true"

+	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
+	register "enable_energy_perf_pref" = "true"
+	register "energy_perf_pref_value" = "0x73"
+
    # Intel Common SoC Config
    register "common_soc_config" = "{
    	.i2c[0] = {
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index c637ec3..a39a481 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -143,6 +143,10 @@
    register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
    register "PchHdaIDispCodecEnable" = "1"

+	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
+	register "enable_energy_perf_pref" = "true"
+	register "energy_perf_pref_value" = "0x73"
+
    # Intel Common SoC Config
    register "common_soc_config" = "{
    	.gspi[1] = {
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index f7da2d1..4028c34 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -127,6 +127,10 @@

register "CnviBtAudioOffload" = "true"

+	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
+	register "enable_energy_perf_pref" = "true"
+	register "energy_perf_pref_value" = "0x73"
+
    # Intel Common SoC Config
    register "common_soc_config" = "{
    	.i2c[0] = {