Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58198 )
Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor ......................................................................
mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
coreboot normally owns PCIe resets for all Cezanne based systems. However during S0i3 resume coreboot cannot intervene for S0 GPIOs (S5 carry over fine) so we needed an alternate way to de-assert this reset on guybrush. This change feeds in the given S0 reset GPIO (69 in this case) so that SMU may de-assert this reset on S0i3 resume.
BUG=b:199780346 TEST=With latest FSP verify SD device trains each of 10 cycles
Cq-Depend: chrome-internal:4157948 Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356 Signed-off-by: Matt Papageorge matthewpapa07@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198 Reviewed-by: Karthik Ramasubramanian kramasub@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index b745fc1..09bded0 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -34,6 +34,7 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, + .gpio_group_id = GPIO_69, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* WWAN */ @@ -116,6 +117,7 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, + .gpio_group_id = GPIO_69, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* WWAN */