[S] Change in coreboot[main]: nb/via/cx700: Perform early bootblock init

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82768?usp=email )

Change subject: nb/via/cx700: Perform early bootblock init
......................................................................

nb/via/cx700: Perform early bootblock init

Disable a timer (GP3) that is always running by default. And enable
SMBus, which is useful this early as a console. The SMBus controller
is mostly compatible to the Intel one.

Change-Id: I77f179433b280d67860fc495605b5764ed081a6c
Signed-off-by: Nico Huber 
---
M src/northbridge/via/cx700/Kconfig
M src/northbridge/via/cx700/Makefile.mk
A src/northbridge/via/cx700/bootblock.c
A src/northbridge/via/cx700/early_smbus.c
4 files changed, 43 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/82768/1

diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig
index 95f289a..f2ba54e 100644
--- a/src/northbridge/via/cx700/Kconfig
+++ b/src/northbridge/via/cx700/Kconfig
@@ -5,6 +5,7 @@
    select PCI
    select NO_ECAM_MMCONF_SUPPORT
    select HAVE_CF9_RESET
+	select SOUTHBRIDGE_INTEL_COMMON_SMBUS

if NORTHBRIDGE_VIA_CX700

diff --git a/src/northbridge/via/cx700/Makefile.mk b/src/northbridge/via/cx700/Makefile.mk
index 550ee2d..a7af6fd 100644
--- a/src/northbridge/via/cx700/Makefile.mk
+++ b/src/northbridge/via/cx700/Makefile.mk
@@ -1,7 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 ifeq ($(CONFIG_NORTHBRIDGE_VIA_CX700),y)

-romstage-y	+= romstage.c
+bootblock-y	+= early_smbus.c bootblock.c
+romstage-y	+= early_smbus.c romstage.c
 ramstage-y	+= chip.c
 all-y		+= clock.c reset.c

diff --git a/src/northbridge/via/cx700/bootblock.c b/src/northbridge/via/cx700/bootblock.c
new file mode 100644
index 0000000..cc048091
--- /dev/null
+++ b/src/northbridge/via/cx700/bootblock.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_ops.h>
+#include <device/smbus_host.h>
+#include <static_devices.h>
+#include <arch/bootblock.h>
+
+#define MISC_CONFIG_1		0x94
+#define  SMBUS_CLOCK_SELECT	(1 << 7)
+
+#define GP2_GP3_TIMER_CONTROL	0x98
+#define  GP3_TIMER_TICK_SELECT	(3 << 4)
+
+#define SMBUS_IO_BASE		0xd0
+#define SMBUS_HOST_CONFIG	0xd2
+#define  SMBUS_CLOCK_FROM_128K	(1 << 2)
+#define  SMBUS_ENABLE		(1 << 0)
+
+int smbus_enable_iobar(uintptr_t base)
+{
+	pci_and_config8(_sdev_lpc, MISC_CONFIG_1, (u8)~SMBUS_CLOCK_SELECT); /* 14.318MHz */
+	pci_write_config16(_sdev_lpc, SMBUS_IO_BASE, base);
+	pci_or_config8(_sdev_lpc, SMBUS_HOST_CONFIG, SMBUS_CLOCK_FROM_128K | SMBUS_ENABLE);
+	return 0;
+}
+
+void bootblock_early_northbridge_init(void)
+{
+	pci_and_config8(_sdev_lpc, GP2_GP3_TIMER_CONTROL, ~GP3_TIMER_TICK_SELECT);
+
+	enable_smbus();
+}
diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c
new file mode 100644
index 0000000..eb8a0f0
--- /dev/null
+++ b/src/northbridge/via/cx700/early_smbus.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/smbus_host.h>
+
+uintptr_t smbus_base(void)
+{
+	return CONFIG_FIXED_SMBUS_IO_BASE;
+}