Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Angel Pons, Subrata Banik, Michael Niewöhner, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Marshall Dawson, Tim Wawrzynczak, Felix Held. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57888 )
Change subject: soc/amd/cezanne,soc/intel/common: rework CPPC table generation ......................................................................
Patch Set 12:
(16 comments)
Patchset:
PS12: Line over 96?
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/57888/comment/e3dd6178_254232ae PS12, Line 108: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/3b39223c_afe7e1fd PS12, Line 110: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/33eb0c55_7adc9de8 PS12, Line 111: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/95a4bb65_1a02f612 PS12, Line 112: config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/f0009844_ea61131c PS12, Line 135: config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10);
line over 96 characters
Please fix.
File src/soc/amd/cezanne/cppc.c:
https://review.coreboot.org/c/coreboot/+/57888/comment/7f6819ef_b5d78c36 PS12, Line 18: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/3b6fa0a6_7cc17044 PS12, Line 19: config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/d5d41f31_f0d35e01 PS12, Line 20: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/866322bf_62d31aec PS12, Line 21: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/6c702356_155fdd5f PS12, Line 23: config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/1ad61c5b_2fc41007 PS12, Line 24: config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/ce9ce022_fd9fe634 PS12, Line 25: config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/ceab9752_f7ce03bb PS12, Line 29: config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/4412e84c_f25b40bb PS12, Line 30: config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/57888/comment/3658a2bc_b5ffbd51 PS12, Line 39: config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
line over 96 characters
Please fix.