[S] Change in coreboot[main]: soc/intel/alderlake: Refactor CrashLog BAR helpers

[Benjamin Doron (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik.

Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81936?usp=email )

Change subject: soc/intel/alderlake: Refactor CrashLog BAR helpers
......................................................................

soc/intel/alderlake: Refactor CrashLog BAR helpers

To enable early CrashLog dumping in bootblock, we cannot use the
resource allocator's helpers. These functions only get the BAR, so just
read it directly from the PCI config space.

Change-Id: Ic4d1d9d19b4b81e5e90f18ae0c03d1c34d3724eb
Signed-off-by: Benjamin Doron 
---
M src/soc/intel/alderlake/Makefile.mk
M src/soc/intel/alderlake/crashlog.c
M src/soc/intel/common/block/pmc/Makefile.mk
3 files changed, 13 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81936/1

diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 55fc83ea..7227e9c 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -16,6 +16,7 @@
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c
 bootblock-y += p2sb.c
+bootblock-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
 bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c

romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c
index 5a08c25..ab2823b 100644
--- a/src/soc/intel/alderlake/crashlog.c
+++ b/src/soc/intel/alderlake/crashlog.c
@@ -33,7 +33,6 @@
 {
    uintptr_t sram_bar;
    const struct device *dev;
-	struct resource *res;

dev = pcidev_path_on_root(PCH_DEVFN_SRAM);
    if (!dev) {
@@ -41,15 +40,13 @@
    	return 0;
    }

-	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
-	if (!res) {
+	sram_bar = pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0) &
+			~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+	if (!sram_bar) {
    	printk(BIOS_ERR, "PCH SRAM device not found!\n");
    	return 0;
    }

-	/* Get the base address of the resource */
-	sram_bar = res->base;
-
    return sram_bar;
 }

@@ -226,6 +223,8 @@

bool cpu_cl_discovery(void)
 {
+	u32 base_addr = 0;
+
    memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t));

if (!cpu_cl_get_capability(&cpu_cl_devsc_cap)) {
@@ -236,8 +235,12 @@

m_cpu_crashLog_support = true;

-	const struct resource *res = find_resource(SA_DEV_TMT, PCI_BASE_ADDRESS_0);
-	printk(BIOS_DEBUG, "cpu crashlog bar addr: 0x%llX\n", res->base);
+	/* Resource may be indicated by the SRAM device. Enable these together. */
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_SRAM);
+	if (dev)
+		base_addr = pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0) &
+				~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+	printk(BIOS_DEBUG, "cpu crashlog bar addr: 0x%X\n", base_addr);

if (!cpu_cl_gen_discovery_table()) {
    	printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n");
diff --git a/src/soc/intel/common/block/pmc/Makefile.mk b/src/soc/intel/common/block/pmc/Makefile.mk
index ea9242b..b50af4f 100644
--- a/src/soc/intel/common/block/pmc/Makefile.mk
+++ b/src/soc/intel/common/block/pmc/Makefile.mk
@@ -7,6 +7,7 @@
 smm-y += pmclib.c
 verstage-y += pmclib.c
 postcar-y += pmclib.c
+bootblock-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc.c
 ramstage-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc.c
 ramstage-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc_acpi.c
 endif