[XS] Change in coreboot[main]: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84085?usp=email )

Change subject: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64
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soc/intel/meteorlake: Configure DDR5 Physical channel width to 64

A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.

This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5
Physical channel width to 64"

Building with GCC LTO cought this buffer overflow when assigning SPD
addresses to a buffer.

Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
---
M src/soc/intel/meteorlake/meminit.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c
index 32ab358..dae175f 100644
--- a/src/soc/intel/meteorlake/meminit.c
+++ b/src/soc/intel/meteorlake/meminit.c
@@ -8,7 +8,7 @@
 #define LPX_PHYSICAL_CH_WIDTH		16
 #define LPX_CHANNELS			CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH)

-#define DDR5_PHYSICAL_CH_WIDTH		32
+#define DDR5_PHYSICAL_CH_WIDTH		64 /* 32*2 */
 #define DDR5_CHANNELS			CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)

static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg)