Attention is currently required from: Matt DeVillier, Tim Wawrzynczak, Sridhar Siricilla, Michael Niewöhner, Lean Sheng Tan, Patrick Rudolph, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61650 )
Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 3:
(4 comments)
File src/soc/intel/skylake/pmc.c:
https://review.coreboot.org/c/coreboot/+/61650/comment/3e8f204b_2bdc6000
PS3, Line 99: pci_or_config32(dev, GEN_PMCON_A, 0);
Understood, then this one should be dropped
Ack
File src/soc/intel/skylake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61650/comment/ce711493_9bef71ae
PS3, Line 269: void pmc_clear_pmcon_sts(void)
> this function is all the same for all platforms using common code, so why exactly do we […]
Ack
https://review.coreboot.org/c/coreboot/+/61650/comment/bc0a90b5_1c99e7ed
PS3, Line 273: addr = pmc_mmio_regs();
:
: reg_val = read32(addr + GEN_PMCON_A);
Oops :(
Ack
https://review.coreboot.org/c/coreboot/+/61650/comment/6d2c7814_1e042146
PS3, Line 276: /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
: * while retaining MS4V write-1-to-clear bit
nit: not a valid comment according to coreboot codestyle docs ;)
Ack
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