Change in coreboot[master]: mb/google/brya: Enable DDR4 SODIMM for brask

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: David Wu, Furquan Shaikh, Paul Menzel, Zhuohao Lee, Alan Huang.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56539 )

Change subject: mb/google/brya: Enable DDR4 SODIMM for brask
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Patch Set 16: Code-Review+2

(3 comments)

Patchset:

PS16: 
Thanks David and Alan!

File src/mainboard/google/brya/chromeos.fmd:

https://review.coreboot.org/c/coreboot/+/56539/comment/5c8769bb_0ab94af3 
PS15, Line 24: 			RW_SPD_CACHE(PRESERVE) 4K
> Ack

Done

File src/mainboard/google/brya/variants/baseboard/brask/memory.c:

https://review.coreboot.org/c/coreboot/+/56539/comment/d9cb1fd1_0bd4232f 
PS15, Line 38: variant_get_spd_info
> We do have called this function in romstage.c.

Sorry, I think I looked at the wrong patchset.