Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM

[Marshall Dawson (Code Review)]

Hello Edward O'Callaghan, Julius Werner, Richard Spiegel, build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33759

to look at the new patch set (#5).

Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
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soc/amd/picasso: Create a hybrid romstage to begin in DRAM

Add the support files to begin execution in romstage and located in
DRAM.  Details for this implementation are found in
Documentation/amd/picasso/family17.md.

Combine steps typically found in bootblock, that contain the reset
vector and set up flat protected mode, with the parts of romstage
that enable the console and cbmem.

Duplicate the ROMSTAGE_ADDR and ROMSTAGE_MAX_SIZE items into Kconfig
and give them safe default values in DRAM.  The DCACHE values are
kept and DRAM is used as a CAR substitute.

Add a romstage.ld file that positions the reset vector and describes
the remaining region for the initial BIOS.

Family 17h doesn't support cache-as-RAM and x86 processors all run
postcar.  Stub the CAR teardown function until postcar is removed.

Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
A src/soc/amd/picasso/exit_car.S
M src/soc/amd/picasso/include/soc/cpu.h
M src/soc/amd/picasso/include/soc/romstage.h
A src/soc/amd/picasso/include/soc/romstage.ld
A src/soc/amd/picasso/reset_vector.S
M src/soc/amd/picasso/romstage.c
8 files changed, 356 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33759/5