Change in coreboot[master]: soc/intel/alderlake: Configure DDR5 Physical channel width to 64

[Meera Ravindranath (Code Review)]

Attention is currently required from: Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Angel Pons, Subrata Banik, Nick Vaccaro, Ronak Kanabar, Patrick Rudolph.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52730 )

Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
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Patch Set 8:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/52730/comment/b47200d8_8d40a557 
PS5, Line 7: mb/intel/adlrvp: Configure DIMM_MAX
> Maybe: […]

Ack

https://review.coreboot.org/c/coreboot/+/52730/comment/908cdf5b_373d2df4 
PS5, Line 9: Adlrvp DDR5 board has 8 DIMM slots(4 channels and 2 DIMMs
           : per channel)
> Please: […]

Ack