Attention is currently required from: Raul Rangel, Rob Barnes, Karthik Ramasubramanian, Felix Held. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 )
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ......................................................................
Patch Set 23:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61259/comment/caa6f798_6cfa9b06 PS20, Line 14: BRANCH
Add a new line between this and the Signed-Off-By
Done
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/5dd3a5b6_b67c204a PS20, Line 152: /* : * The remapping of values is done so that the default of the enum used for the : * devicetree settings is the clock being enabled, so that a missing devicetree : * configuration for this will result in an always active clock and not an : * inactive PCIe clock output. : */
we should keep this comment, since what it points out isn't very obvious
Done
https://review.coreboot.org/c/coreboot/+/61259/comment/1d2bf931_f7d98a58 PS20, Line 21: #include "include/soc/platform_descriptors.h"
this should be #include <soc/platform_descriptors. […]
Done
https://review.coreboot.org/c/coreboot/+/61259/comment/036b0d36_ee86da84 PS20, Line 187: CLK_ENABLE
this should probably be CLK_DISABLE
Done
https://review.coreboot.org/c/coreboot/+/61259/comment/a290546e_26c59b16 PS20, Line 188: 1
replacing this 1 with CLK_REQ0 would at least for me make this line easier to understand
Done