New patch to review for coreboot: device/dram: use global DIMM_SPD_SIZE Kconfig variable
Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18254
-gerrit
commit 1fcf72bf578e1990c1e1057ea6cbe9d5ee1c7eee Author: Patrick Georgi pgeorgi@chromium.org Date: Sat Jan 28 13:12:09 2017 +0100
device/dram: use global DIMM_SPD_SIZE Kconfig variable
Also make sure that no board changes behaviour because of that by adding a static assert.
TEST=abuild over all builds still succeeds (where it doesn't if DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the device/dram code).
Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449 Signed-off-by: Patrick Georgi pgeorgi@chromium.org --- src/device/dram/spd_cache.c | 10 ++++++---- src/mainboard/amd/db-ft3b-lc/Kconfig | 4 ++++ src/mainboard/bap/ode_e20XX/Kconfig | 4 ++++ src/mainboard/bap/ode_e21XX/Kconfig | 4 ++++ src/mainboard/gizmosphere/gizmo/Kconfig | 4 ++++ src/mainboard/gizmosphere/gizmo2/Kconfig | 4 ++++ src/mainboard/pcengines/apu1/Kconfig | 4 ++++ src/mainboard/pcengines/apu2/Kconfig | 4 ++++ 8 files changed, 34 insertions(+), 4 deletions(-)
diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index c7dd97d..3bdd9c1 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -25,11 +25,13 @@ #define SPD_CRC_HI 127 #define SPD_CRC_LO 126
+_Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ"); + int read_spd_from_cbfs(u8 *buf, int idx) { const char *spd_file; size_t spd_file_len = 0; - size_t min_len = (idx + 1) * SPD_SIZE; + size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE;
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); @@ -40,9 +42,9 @@ int read_spd_from_cbfs(u8 *buf, int idx) if (!spd_file || spd_file_len < min_len) return -1;
- memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE); + memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE);
- u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE); + u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE);
if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) || (buf[SPD_CRC_LO] != (crc & 0xff)) @@ -53,7 +55,7 @@ int read_spd_from_cbfs(u8 *buf, int idx) buf[SPD_CRC_HI] = crc >> 8; u16 i; printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < SPD_SIZE; i++) { + for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { if((i % 16) == 0x00) printk(BIOS_WARNING, "\n%02x: ", i); printk(BIOS_WARNING, "%02x ", buf[i]); diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index ace741d..7bf3c86 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -53,4 +53,8 @@ config HUDSON_LEGACY_FREE bool default y
+config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_AMD_DB_FT3B_LC diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index ad1c3de..ee26772 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -80,4 +80,8 @@ config BAP_E20_DDR3_1066
endchoice
+config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_ODE_E20XX diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index b356749..60a59ac 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -74,4 +74,8 @@ config BAP_E21_DDR3_1333
endchoice
+config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_ODE_E21XX diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 0c78f79..8109019 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -70,4 +70,8 @@ config SB800_AHCI_ROM bool default n
+config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_GIZMOSPHERE_GIZMO diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 55beca6..349f827 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -61,4 +61,8 @@ config HUDSON_LEGACY_FREE bool default y
+config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_GIZMOSPHERE_GIZMO2 diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3099d14..f882b78 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -116,4 +116,8 @@ endchoice config UART_D_RS485 bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D
+config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 0acf416..de42721 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -88,4 +88,8 @@ config APU2_PINMUX_UART_D
endchoice
+config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_PCENGINES_APU2
-
Patrick Georgi