Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Martin Roth, Tim Van Patten.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75699?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/myst: Update PCIe romstage gpios ......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3: have you checked if the time between the reset being deasserted and the pcie training in fsp to begin is less than 20ms? i wonder if we should move the deasserting of PCIE_RSTx_L into pcie init in FSP to make sure that the timing requirements are always met and only do the aux reset configuration in coreboot. currently discussing this internally in a slightly different context
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/5ea7daea_ff55555f : PS3, Line 199: /* PCIE_RST0_L */ : PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), i'd move deaserting the main reset line to the end of the table so that it'll be done as the last step
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Felix Held (Code Review)