Change in coreboot[master]: intel/common/block/cse: Add option to send EOP early via SoC

[Maulik V Vaghela (Code Review)]

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Patrick Rudolph.
Hello build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Sridhar Siricilla, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60195

to look at the new patch set (#12).

Change subject: intel/common/block/cse: Add option to send EOP early via SoC
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intel/common/block/cse: Add option to send EOP early via SoC

Earlier while trying to optimize boot time End Of Post (EOP) time kept
increasing (~80 ms) when boot time decreased to around 1 second.
This was because CSE was busy with own firmware loading.

When EOP was moved later in boot stage it again created issue since CSE
got busy with other payload loading for OS boot, so response to EOP
got delayed by ~70-80 ms.

In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow
where FSP used to send EOP once silicon init is done and coreboot used
to rely on FSP to send this message.

Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP
time reduces from ~60 ms to ~20 ms on Brya QS board.

Since this setting might vary for each SoC, SoCs can decide when to send
EOP in the boot sequence. This patch adds Kconfig option to send EOP via
SoC

BUG=b:211085685
BRANCH=firmware-brya-14505.B
TEST=Code compilation is fine for Brya board. Boot time test is done
using entire patchset and EOP time is reduced to ~25ms from earlier ~80ms.

Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35
Signed-off-by: MAULIK V VAGHELA 
---
M src/soc/intel/common/block/cse/Kconfig
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/60195/12