Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45096 )
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
vc/amd/fsp/picasso: Update to UPD 1.0.1.3
BUG=b:159823235 TEST=Build test
Cq-Depend: chrome-internal:3251807 Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2 --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45096/1
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 5adbb81..b9f9a3b 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -15,7 +15,8 @@
typedef struct __packed { /** Offset 0x0020**/ uint32_t emmc0_mode; - /** Offset 0x0024**/ uint8_t unused0[12]; + /** Offset 0x0024**/ uint8_t emmc0_drive_strength; + /** Offset 0x0025**/ uint8_t unused0[11]; /** Offset 0x0030**/ uint8_t dxio_descriptor[FSPS_UPD_DXIO_DESCRIPTOR_COUNT][16]; /** Offset 0x00B0**/ uint8_t unused1[16]; /** Offset 0x00C0**/ uint32_t ddi_descriptor[FSPS_UPD_DDI_DESCRIPTOR_COUNT]; @@ -31,7 +32,8 @@ /** Offset 0x011D**/ uint8_t unused3; /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; /** Offset 0x0122**/ uint8_t xhci0_force_gen1; - /** Offset 0x0123**/ uint8_t UnusedUpdSpace0[45]; + /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x0124**/ uint8_t UnusedUpdSpace0[44]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG;
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45096 )
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45096/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45096/1//COMMIT_MSG@8 PS1, Line 8: Please summarize the changes in the commit message.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45096 )
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45096/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/FspsUpd.h:
https://review.coreboot.org/c/coreboot/+/45096/1/src/vendorcode/amd/fsp/pica... PS1, Line 35: /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; : /** Offset 0x0124**/ uint8_t UnusedUpdSpace0[44]; these should go away due to CB:45113 once you rebase.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45096 )
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
Patch Set 1:
Need a rebase.
Hello build bot (Jenkins), Furquan Shaikh, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45096
to look at the new patch set (#2).
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
vc/amd/fsp/picasso: Update to UPD 1.0.1.3
This adds eMMC preset settings.
It also fixes some formatting and a comment.
BUG=b:159823235 TEST=Build test
Cq-Depend: chrome-internal:3251807 Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2 --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 9 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45096/2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45096 )
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45096/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45096/1//COMMIT_MSG@8 PS1, Line 8:
Please summarize the changes in the commit message.
Done
https://review.coreboot.org/c/coreboot/+/45096/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/FspsUpd.h:
https://review.coreboot.org/c/coreboot/+/45096/1/src/vendorcode/amd/fsp/pica... PS1, Line 35: /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; : /** Offset 0x0124**/ uint8_t UnusedUpdSpace0[44];
these should go away due to CB:45113 once you rebase.
Done
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45096 )
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
Patch Set 2: Code-Review+2
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45096 )
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
Patch Set 2: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45096 )
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
vc/amd/fsp/picasso: Update to UPD 1.0.1.3
This adds eMMC preset settings.
It also fixes some formatting and a comment.
BUG=b:159823235 TEST=Build test
Cq-Depend: chrome-internal:3251807 Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45096 Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 9 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index c1d3db0..491ea47 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -15,7 +15,11 @@
typedef struct __packed { /** Offset 0x0020**/ uint32_t emmc0_mode; - /** Offset 0x0024**/ uint8_t unused0[12]; + /** Offset 0x0024**/ uint16_t emmc0_init_khz_preset; + /** Offset 0x0026**/ uint8_t emmc0_sdr104_hs400_driver_strength; + /** Offset 0x0027**/ uint8_t emmc0_ddr50_driver_strength; + /** Offset 0x0028**/ uint8_t emmc0_sdr50_driver_strength; + /** Offset 0x0029**/ uint8_t unused0[7]; /** Offset 0x0030**/ uint8_t dxio_descriptor[FSPS_UPD_DXIO_DESCRIPTOR_COUNT][16]; /** Offset 0x00B0**/ uint8_t unused1[16]; /** Offset 0x00C0**/ uint32_t ddi_descriptor[FSPS_UPD_DDI_DESCRIPTOR_COUNT]; @@ -32,10 +36,10 @@ /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; /** Offset 0x0122**/ uint8_t xhci0_force_gen1; /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; - /** Offset 0x0124**/ uint32_t gnb_ioapic_base; - /** Offset 0x0128**/ uint8_t gnb_ioapic_id; - /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x0126**/ uint8_t UnusedUpdSpace0[38]; + /** Offset 0x0124**/ uint32_t gnb_ioapic_base; + /** Offset 0x0128**/ uint8_t gnb_ioapic_id; + /** Offset 0x0129**/ uint8_t fch_ioapic_id; + /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[38]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG;