Change in coreboot[master]: mb/google/dedede/var/kracko: refactor DPTF section for overrides

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57828 )

Change subject: mb/google/dedede/var/kracko: refactor DPTF section for overrides
......................................................................

mb/google/dedede/var/kracko: refactor DPTF section for overrides

Refactor DPTF section of code under the kracko overridetree. This makes kracko override dptf section of dedede/baseboard, because the DPTF tool's CRT, PSV and TSR3 settings are different than expected.

BUG=b:187482019
BRANCH=dedede
TEST=Built and tested on dedede system

Change-Id: Iacc543f961a7f4652ee8583920b1794f916c7ec9
Signed-off-by: Robert Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57828
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/dedede/variants/kracko/overridetree.cb
1 file changed, 56 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
index 36226de..2124103 100644
--- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
@@ -58,7 +58,63 @@
    	},
    }"

+	register "power_limits_config" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+	}"
+
+	register "tcc_offset" = "20"	# TCC of 85C
+
    device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				# Default DPTF Policy for all drawcia boards if not overridden
+				register "options.tsr[0].desc" = ""Memory""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""5V regulator""
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,		CPU,	       80, 1000),
+					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 70, 4000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 51, 1000),
+					[3] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_2, 75, 5000),
+					[4] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_3, 60, 1000)
+				}"
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,           119, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 115, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN)
+				}"
+				register "controls.power_limits" = "{
+					.pl1 = {
+						.min_power = 3800,
+						.max_power = 5800,
+						.time_window_min = 1 * MSECS_PER_SEC,
+						.time_window_max = 1 * MSECS_PER_SEC,
+						.granularity = 200,
+					},
+					.pl2 = {
+						.min_power = 20000,
+						.max_power = 20000,
+						.time_window_min = 1 * MSECS_PER_SEC,
+						.time_window_max = 1 * MSECS_PER_SEC,
+						.granularity = 1000,
+					}
+				}"
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 3000 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+				device generic 0 alias dptf_policy on end
+			end
+		end # SA Thermal device
    	device pci 14.0 on
    		chip drivers/usb/acpi
    			device usb 0.0 on