Change in coreboot[master]: soc/intel/alderlake: Allow thermal configuration for ADL

[Subrata Banik (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai.
Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/59271

to look at the new patch set (#3).

Change subject: soc/intel/alderlake: Allow thermal configuration for ADL
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soc/intel/alderlake: Allow thermal configuration for ADL

Thermal configuration registers are now located behind PMC PWRMBASE
for Alder Lake Point PCH. Hence, ADL SoC to select
SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold
is being set as per mainboard provided `pch_thermal_trip`.

Note: These thermal configuration registers are RW/O hence, setting
those early prior to FSP-S helps coreboot to set the desired low
thermal threshold for the platform.

BUG=b:193774296
TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior
to FSP-S shows that registers are now programmed based on
'pch_thermal_trip' and lock register BIT31 is set.

Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.c
2 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/59271/3