Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55413 )
Change subject: cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER ......................................................................
cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER
Leftover from using UDELAY_LAPIC on these platforms.
Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c 7 files changed, 0 insertions(+), 33 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 3e4de1f..33187d7 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -12,18 +12,6 @@
#include "chip.h"
-static void init_timer(void) -{ - /* Set the APIC timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17) | (1 << 16) | (0 << 12) | (0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); -} - #define MSR_BBL_CR_CTL3 0x11e
static void configure_c_states(const int quad) @@ -271,9 +259,6 @@ /* Enable the local CPU APICs */ setup_lapic();
- /* Initialize the APIC timer */ - init_timer(); - /* Configure C States */ configure_c_states(quad);
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index b87380a..744c92b 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <cpu/x86/lapic.h> #include <arch/romstage.h> #include <northbridge/intel/gm45/gm45.h> #include <southbridge/intel/i82801ix/i82801ix.h> @@ -42,8 +41,6 @@ /* basic northbridge setup, including MMCONF BAR */ gm45_early_init();
- enable_lapic(); - /* First, run everything needed for console output. */ i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 28a0c79..4980f9b 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <device/mmio.h> #include <elog.h> -#include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include <security/intel/txt/txt.h> #include <security/intel/txt/txt_register.h> @@ -20,8 +19,6 @@ /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { - enable_lapic(); - early_pch_init();
/* Perform some early chipset initialization required diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index efcf0d6..0a61780 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -2,7 +2,6 @@
#include <stdint.h> #include <cf9_reset.h> -#include <cpu/x86/lapic.h> #include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -30,8 +29,6 @@ int s3resume = 0; u8 spd_map[4] = {};
- enable_lapic(); - mainboard_lpc_decode();
if (mchbar_read16(SSKPD) == 0xcafe) { diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 8d3cfd6..242100b 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <cf9_reset.h> #include <device/pci_ops.h> -#include <cpu/x86/lapic.h> #include <timestamp.h> #include <romstage_handoff.h> #include "ironlake.h" @@ -27,8 +26,6 @@ int s3resume = 0; u8 spd_addrmap[4] = {};
- enable_lapic(); - /* TODO, make this configurable */ ironlake_early_initialization(IRONLAKE_MOBILE);
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 5e5420c..a98ae99 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -9,7 +9,6 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/pmclib.h> #include <arch/romstage.h> -#include <cpu/x86/lapic.h> #include "raminit.h" #include "pineview.h"
@@ -31,8 +30,6 @@ int boot_path, cbmem_was_initted; int s3resume = 0;
- enable_lapic(); - /* Do some early chipset init, necessary for RAM init to work */ i82801gx_early_init(); pineview_early_init(); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 71b8e12..a6f626a 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <cf9_reset.h> #include <device/pci_ops.h> -#include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include "sandybridge.h" #include <arch/romstage.h> @@ -54,8 +53,6 @@ if (mchbar_read16(SSKPD_HI) == 0xcafe) system_reset();
- enable_lapic(); - /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init();
-
Kyösti Mälkki (Code Review)