Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68927 )
Change subject: soc/amd/common: Initialize STB Spill-to-DRAM ......................................................................
soc/amd/common: Initialize STB Spill-to-DRAM
Signed-off-by: Martin Roth gaumless@gmail.com Change-Id: I547671d2bcfe011566466665b14e151b8ec05430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68927 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Fred Reitberger reitbergerfred@gmail.com Reviewed-by: Jason Glenesk jason.glenesk@gmail.com --- M src/soc/amd/common/block/include/amdblocks/stb.h M src/soc/amd/common/block/smu/Makefile.inc M src/soc/amd/common/block/stb/Kconfig M src/soc/amd/common/block/stb/stb.c 4 files changed, 68 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Fred Reitberger: Looks good to me, approved
diff --git a/src/soc/amd/common/block/include/amdblocks/stb.h b/src/soc/amd/common/block/include/amdblocks/stb.h index c8851f8..db032b9 100644 --- a/src/soc/amd/common/block/include/amdblocks/stb.h +++ b/src/soc/amd/common/block/include/amdblocks/stb.h @@ -16,7 +16,6 @@ };
void write_stb_to_console(void); -void init_spill_buffer(void); void add_stb_to_timestamp_buffer(void);
#endif /* AMD_BLOCK_STB_H */ diff --git a/src/soc/amd/common/block/smu/Makefile.inc b/src/soc/amd/common/block/smu/Makefile.inc index 2afd81a..13720a3 100644 --- a/src/soc/amd/common/block/smu/Makefile.inc +++ b/src/soc/amd/common/block/smu/Makefile.inc @@ -1 +1,4 @@ smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c diff --git a/src/soc/amd/common/block/stb/Kconfig b/src/soc/amd/common/block/stb/Kconfig index fe2b5b7..28c78fd 100644 --- a/src/soc/amd/common/block/stb/Kconfig +++ b/src/soc/amd/common/block/stb/Kconfig @@ -1,6 +1,7 @@ config SOC_AMD_COMMON_BLOCK_STB bool select SOC_AMD_COMMON_BLOCK_SMN + select SOC_AMD_COMMON_BLOCK_SMU help Select in the SOC if it supports the Smart Trace Buffer
@@ -9,11 +10,28 @@ config WRITE_STB_BUFFER_TO_CONSOLE bool "Write STB entries to the console log" default n + depends on !ENABLE_STB_SPILL_TO_DRAM help This option will tell coreboot to print the STB buffer at various points through the boot process. Note that this will prevent the entries from being stored if the Spill-to-DRAM feature is enabled.
+config ENABLE_STB_SPILL_TO_DRAM + bool "Enable Smart Trace Buffer Spill-to-DRAM" + default n + help + Spill-to-DRAM is an STB feature that extends the buffer from using + just the small SRAM buffer to a much larger area reserved in main + memory. + +config AMD_STB_SIZE_IN_MB + int "Smart Trace Buffer Spill-to-DRAM buffer size in MB" + default 3 + range 3 16 + depends on ENABLE_STB_SPILL_TO_DRAM + help + Size of the STB Spill-to-DRAM buffer in MB. + config ADD_POSTCODES_TO_STB bool "Add coreboot postcodes to STB" default y diff --git a/src/soc/amd/common/block/stb/stb.c b/src/soc/amd/common/block/stb/stb.c index 0cea5c3..934a49b 100644 --- a/src/soc/amd/common/block/stb/stb.c +++ b/src/soc/amd/common/block/stb/stb.c @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include "commonlib/bsd/cb_err.h" #include <amdblocks/smn.h> +#include <amdblocks/smu.h> #include <amdblocks/stb.h> #include <bootstate.h> +#include <cbmem.h> #include <console/console.h> +#include <soc/smu.h> #include <soc/stb.h>
#define STB_ENTRIES_PER_ROW 4 @@ -59,9 +63,37 @@ if ((i % STB_ENTRIES_PER_ROW) == STB_ENTRIES_PER_ROW - 1) printk(BIOS_DEBUG, "\n"); printed_data = 1; + } +}
+static void init_spill_buffer(void *unused) +{ + struct smu_payload smu_payload = {0}; + uintptr_t stb; + uint32_t size = CONFIG_AMD_STB_SIZE_IN_MB * MiB; + int i; + + if (!CONFIG(ENABLE_STB_SPILL_TO_DRAM)) + return; + + stb = (uintptr_t)cbmem_add(CBMEM_ID_AMD_STB, size); + if (!stb) { + printk(BIOS_ERR, "Could not allocate cbmem buffer for STB\n"); + return; }
+ smu_payload.msg[0] = (uint32_t)stb; + smu_payload.msg[1] = 0; + smu_payload.msg[2] = size; + + printk(BIOS_DEBUG, "STB spill buffer: allocated %d MiB at %lx\n", + CONFIG_AMD_STB_SIZE_IN_MB, stb); + + if (send_smu_message(SMC_MSG_SET_S2D_ADDR, &smu_payload) == CB_ERR) + printk(BIOS_ERR, "Could not enable STB Spill-to-dram\n"); + + for (i = 0; i < SMU_NUM_ARGS; i++) + printk(BIOS_DEBUG, "smu_payload.msg[%d]: 0x%x\n", i, smu_payload.msg[i]); }
static void final_stb_console(void *unused) @@ -70,4 +102,5 @@ write_stb_to_console(); }
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, init_spill_buffer, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, final_stb_console, NULL);