Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: [WIP] jasperlake: enable DPTF functionality for dedede ......................................................................
[WIP] jasperlake: enable DPTF functionality for dedede
Enable DPTF functionality on jasperlake based dedede platform
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/variants/baseboard/devicetree.cb A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl 7 files changed, 81 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/41668/1
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 6137f3b..3e99651 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -51,4 +51,15 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + /* Dynamic Platform Thermal Framework */ + Scope (_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/common/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } } diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c891e6e..b7aee82 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -133,6 +133,16 @@ register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1"
+ # Enable DPTF + register "dptf_enable" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "Device4Enable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000..f9eebe8 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Below values might change after Thermal Tuning. */ +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Memory" +#define DPTF_TSR0_PASSIVE 80 +#define DPTF_TSR0_CRITICAL 90 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 80 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 1 */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 6000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl>
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Tim Wawrzynczak, Karthikeyan Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41668
to look at the new patch set (#2).
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
jasperlake: enable DPTF functionality for dedede
Enable DPTF functionality on jasperlake based dedede platform
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/variants/baseboard/devicetree.cb A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl 7 files changed, 81 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/41668/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 144: register "Device4Enable" = "1" Can we add a comment that Device4 is DTT (AKA DPTF)?
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 35: 1000, /* TimeWindowMinimum */ : 1000, /* TimeWindowMaximum */ Power limits averaged over a 1 second window? Is that normal for the small cores?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 35: 1000, /* TimeWindowMinimum */ : 1000, /* TimeWindowMaximum */
Power limits averaged over a 1 second window? Is that normal for the small cores?
You set it to MOBILE_SKU_PL1_TIME_SEC in the previous CL
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 185: off off -> on?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 144: register "Device4Enable" = "1"
Can we add a comment that Device4 is DTT (AKA DPTF)?
Ack
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 43: 15000 Also in the devictree.cb PL2 is configured as 20 W whereas here it is 15 W. Should they be consistent or not?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 2:
Patch Set 2:
(1 comment)
Also couple more variants got added - boten and drawcia. They need to be updated as well.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 144: register "Device4Enable" = "1"
Ack
Done
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 185: off
off -> on?
Done
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 35: 1000, /* TimeWindowMinimum */ : 1000, /* TimeWindowMaximum */
You set it to MOBILE_SKU_PL1_TIME_SEC in the previous CL
Ack
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 43: 15000
Also in the devictree.cb PL2 is configured as 20 W whereas here it is 15 W. […]
Ack. It should be 20 W. I have submitted the updated patch for this.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Tim Wawrzynczak, Karthikeyan Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41668
to look at the new patch set (#3).
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
jasperlake: enable DPTF functionality for dedede
Enable DPTF functionality on jasperlake based dedede platform
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/variants/baseboard/devicetree.cb A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/dedede/variants/boten/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl 9 files changed, 87 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/41668/3
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 57: #include <soc/intel/common/acpi/dptf.asl> I think dropping this file is the cause of the build failure.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/41668/2/src/mainboard/google/dedede... PS2, Line 57: #include <soc/intel/common/acpi/dptf.asl>
I think dropping this file is the cause of the build failure.
I had submitted patchset 3 as below, not sure what happened here. https://review.coreboot.org/c/coreboot/+/41668/3/src/mainboard/google/dedede...
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 5:
ping
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
You don't want to wait until my DPTF patches have landed? 😉
https://review.coreboot.org/c/coreboot/+/41668/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41668/5//COMMIT_MSG@10 PS5, Line 10: Mention PL1 & PL2 as well?
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 5:
(1 comment)
Patch Set 5: Code-Review+2
(1 comment)
You don't want to wait until my DPTF patches have landed? 😉
I would like to wait and get those in as well, but I have heard some thermal issues so wanted to get this merge asap to avoid any thermal abrupt shutdown issues. Thanks.
https://review.coreboot.org/c/coreboot/+/41668/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41668/5//COMMIT_MSG@10 PS5, Line 10:
Mention PL1 & PL2 as well?
Done
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
Patch Set 5: Code-Review+2
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41668 )
Change subject: jasperlake: enable DPTF functionality for dedede ......................................................................
jasperlake: enable DPTF functionality for dedede
Enable DPTF functionality on jasperlake based dedede platform
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/variants/baseboard/devicetree.cb A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/dedede/variants/boten/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl 9 files changed, 87 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 933ca1a..e064d9b 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -55,4 +55,13 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + /* Dynamic Platform Thermal Framework */ + Scope (_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } } diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 7fdf438..f95d123 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -144,6 +144,17 @@ # Enable Speed Shift Technology support register "speed_shift_enable" = "1"
+ # Enable DPTF + register "dptf_enable" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + # Enable processor thermal control + register "Device4Enable" = "1" + # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: @@ -153,7 +164,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device + device pci 04.0 on end # SA Thermal device device pci 05.0 off end # IPU device pci 09.0 off end # Intel Trace Hub device pci 12.6 off end # GSPI 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000..f6b16b4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Below values might change after Thermal Tuning. */ +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Memory" +#define DPTF_TSR0_PASSIVE 80 +#define DPTF_TSR0_CRITICAL 90 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 80 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 1 */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 6000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 20000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/dedede/variants/boten/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/boten/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl>
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Karthik Ramasubramanian (Code Review) -
Sumeet R Pawnikar (Code Review)
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Tim Wawrzynczak (Code Review)