Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim.
Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email )
Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Subrata, Here is the response from our EDS owner:
Aux Biasing isolation control is only required for USB3 + DP retimer-less topology. The USB3 + DP configuration is not POR for PTL segment
Looks like you are bringing one more requirement here. In future there might be OxM designs with and without Retimer chip (Retimer is POR for CrOS for sure but that doesn't mean other can't have design w/o Retimer, for example: chromebase doesn't have retimer). Now to meet both such design req and SoC guidelines, you need to introduce a newer kconfig `SOC_INTEL_COMMON_TCSS_SKIP_AUX_PAD` (something meaningful). This stays enable by default and only set to `n` depending on the main board design assumes PTL, fatcat would override it to `N.
Inside aux programming in TCSS file, you should check if SOC_INTEL_COMMON_TCSS_SKIP_AUX_PAD is set then skip the programming.
If agree, we can just let .configure_aux_bias_pads unconfigured in PTL tcss.c and remove all the virtual wire mapping in PTL gpio.c. Please let me know.
This doesn't have any relation if we wish to update the EDS or not. EDS has to be updated irrespective if CrOS is using or not. this is SOC req.