Change in coreboot[master]: soc/intel/common/cse: Add `send_end_of_post_to_cse()` a public function

[Subrata Banik (Code Review)]

Attention is currently required from: Patrick Rudolph.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61519 )

Change subject: soc/intel/common/cse: Add `send_end_of_post_to_cse()` a public function
......................................................................

soc/intel/common/cse: Add `send_end_of_post_to_cse()` a public function

This patch creates a global function `send_end_of_post_to_cse()` so
that IA common code may get access to this function for sending EOP
command to the HECI1/CSE device.

BUG=b:211954778
TEST=Able to build and boot Brya.

Signed-off-by: Subrata Banik 
Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc
---
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/61519/1

diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c
index 3fc4e2b..ce6590d 100644
--- a/src/soc/intel/common/block/cse/cse_eop.c
+++ b/src/soc/intel/common/block/cse/cse_eop.c
@@ -205,6 +205,11 @@
    set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE);
 }

+void send_end_of_post_to_cse(void)
+{
+	return set_cse_end_of_post(NULL);
+}
+
 /*
  * Ideally, to give coreboot maximum flexibility, sending EOP would be done as
  * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 3d99b5c..d73bf38 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -492,6 +492,9 @@
 /* Set CSE device state to D0I3 */
 void cse_set_to_d0i3(void);

+/* Send End of Post (EOP) command to CSE device */
+void send_end_of_post_to_cse(void);
+
 /*
  * SoC override API to make heci1 disable using PCR.
  *