[S] Change in coreboot[master]: soc/cavium/cn81xx: Use correct size for MSR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74538 )

Change subject: soc/cavium/cn81xx: Use correct size for MSR
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soc/cavium/cn81xx: Use correct size for MSR

Clang complains about this.

Change-Id: I2d761d2fa946f171033220ab7b2e399cf359782a
Signed-off-by: Arthur Heymans 
---
M src/soc/cavium/cn81xx/cpu.c
1 file changed, 13 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/74538/1

diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c
index 43b64d5..9ed20d0 100644
--- a/src/soc/cavium/cn81xx/cpu.c
+++ b/src/soc/cavium/cn81xx/cpu.c
@@ -35,7 +35,7 @@

size_t cpu_self_get_core_id(void)
 {
-	u32 mpidr_el1;
+	u64 mpidr_el1;
    asm("mrs %0, MPIDR_EL1\n\t" : "=r" (mpidr_el1) :: "memory");

/* Core is 4 bits from AFF0 and rest from AFF1 */