Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Tim Chu.
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80093?usp=email )
Change subject: soc/intel/xeon_sp/spr: Locate PCU by PCI device ID ......................................................................
soc/intel/xeon_sp/spr: Locate PCU by PCI device ID
Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree.
Intel Document-ID: 735086 Intel Document-ID: 612246
Change-Id: I06694715cba76b101165f1cef66d161b0f896b26 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h 4 files changed, 60 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/80093/1
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index e602ad7..3a03d60 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -115,33 +115,34 @@
static void set_pcu_locks(void) { - for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + struct device *dev = NULL;
- /* configure PCU_CR0_FUN csrs */ - const struct device *cr0_dev = PCU_DEV_CR0(bus); - pci_or_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); - pci_or_config32(cr0_dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PKG_PWR_LIM_LOCK_UPR); - pci_or_config32(cr0_dev, PCU_CR0_TURBO_ACTIVATION_RATIO, TURBO_ACTIVATION_RATIO_LOCK); - - - /* configure PCU_CR1_FUN csrs */ - const struct device *cr1_dev = PCU_DEV_CR1(bus); - pci_or_config32(cr1_dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); - - /* configure PCU_CR2_FUN csrs */ - const struct device *cr2_dev = PCU_DEV_CR2(bus); - pci_or_config32(cr2_dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, PP_PWR_LIM_LOCK); - pci_or_config32(cr2_dev, PCU_CR2_DRAM_POWER_INFO_UPR, DRAM_POWER_INFO_LOCK_UPR); - - /* configure PCU_CR3_FUN csrs */ - const struct device *cr3_dev = PCU_DEV_CR3(bus); - pci_or_config32(cr3_dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); - pci_or_config32(cr3_dev, PCU_CR3_FLEX_RATIO, OC_LOCK); + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { + pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); + pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, + PKG_PWR_LIM_LOCK_UPR); + pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO, + TURBO_ACTIVATION_RATIO_LOCK); }
+ dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) { + pci_or_config32(dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); + } + + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { + pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, + PP_PWR_LIM_LOCK); + pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR, + DRAM_POWER_INFO_LOCK_UPR); + } + + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) { + pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + pci_or_config32(cr3_dev, PCU_CR3_FLEX_RATIO, OC_LOCK); + } }
static void set_imc_locks(void) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 55268a7..7dbe5ee 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -24,6 +24,7 @@ #define PCU_DEV 30
#define PCU_CR0_FUN 0 +#define PCU_CR0_DEVID 0x344a #define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 @@ -37,6 +38,7 @@ #define PMAX_LOCK BIT(31)
#define PCU_CR1_FUN 1 +#define PCU_CR1_DEVID 0x344b #define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c
@@ -64,6 +66,7 @@ #define SAPMCTL_LOCK_MASK BIT(31)
#define PCU_CR2_FUN 2 +#define PCU_CR2_DEVID 0x344c #define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) @@ -72,6 +75,7 @@ #define PP_PWR_LIM_LOCK BIT(31)
#define PCU_CR3_FUN 3 +#define PCU_CR3_DEVID 0x344d #define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0x60 #define TDP_LOCK BIT(31) diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index 3c3417e..8fe9f09 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -80,45 +80,37 @@ } }
-static void pcu_pci_or_config32(u8 bus, u8 func, u32 reg, u32 orval) -{ - u32 data; - const uint32_t pcie_offset = PCI_DEV(bus, PCU_DEV, func); - - data = pci_s_read_config32(pcie_offset, reg); - data |= orval; - pci_s_write_config32(pcie_offset, reg, data); -} - static void set_pcu_locks(void) { - for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - const uint32_t bus = get_ubox_busno(socket, UNCORE_BUS_1); + struct device *dev = NULL;
- /* configure PCU_CR0_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_P_STATE_LIMITS, - P_STATE_LIMITS_LOCK); - pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, - PKG_PWR_LIM_LOCK_UPR); - pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_TURBO_ACTIVATION_RATIO, - TURBO_ACTIVATION_RATIO_LOCK); + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { + pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); + pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, + PKG_PWR_LIM_LOCK_UPR); + pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO, + TURBO_ACTIVATION_RATIO_LOCK); + }
- /* configure PCU_CR2_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_POWER_INFO_UPR, - DRAM_POWER_INFO_LOCK_UPR); - pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR, - PP_PWR_LIM_LOCK_UPR); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { + pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR, + DRAM_POWER_INFO_LOCK_UPR); + pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR, + PP_PWR_LIM_LOCK_UPR); + }
- /* configure PCU_CR3_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR3_FUN, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) { + pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + }
- /* configure PCU_CR6_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR, - PLT_PWR_LIM_LOCK_UPR); - pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR, - PLT_PWR_INFO_LOCK_UPR); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR6_DEVID, dev))) { + pci_or_config32(dev, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR, + PLT_PWR_LIM_LOCK_UPR); + pci_or_config32(dev, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR, + PLT_PWR_INFO_LOCK_UPR); } }
diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 06ec16c..9075728 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -48,6 +48,7 @@ #define PCU_DEV 30
#define PCU_CR0_FUN 0 +#define PCU_CR0_DEVID 0x3258 #define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 @@ -63,6 +64,7 @@ #define VR_CURRENT_CONFIG_LOCK BIT(31)
#define PCU_CR1_FUN 1 +#define PCU_CR1_DEVID 0x3259 #define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c
@@ -87,6 +89,7 @@ #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31)
#define PCU_CR2_FUN 2 +#define PCU_CR2_DEVID 0x325a #define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) @@ -97,6 +100,7 @@ #define PP_PWR_LIM_LOCK_UPR BIT(31)
#define PCU_CR3_FUN 3 +#define PCU_CR3_DEVID 0x325b #define PCU_CR3_CAPID4 0x94 #define ERR_SPOOFING_DIS 1 #define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) @@ -106,6 +110,7 @@ #define OC_LOCK BIT(20)
#define PCU_CR4_FUN 4 +#define PCU_CR4_DEVID 0x325c #define PCU_VIRAL_CONTROL 0x84 #define PCU_FW_ERR_EN (1 << 10) #define PCU_UC_ERR_EN (1 << 9) @@ -113,6 +118,7 @@ #define PCU_EMCA_MODE (1 << 2)
#define PCU_CR6_FUN 6 +#define PCU_CR6_DEVID 0x325e #define PCU_DEV_CR6(bus) _PCU_DEV(bus, PCU_CR6_FUN) #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR 0xa8 #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR (PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR + 4)