Change in coreboot[master]: mb/google/octopus: Edge trigger cr50 interrupt

[Justin TerAvest (Code Review)]

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/25538

Change subject: mb/google/octopus: Edge trigger cr50 interrupt
......................................................................

mb/google/octopus: Edge trigger cr50 interrupt

Interrupts from cr50 are edge-triggered, not level-triggered. This
change updates the GPIO configuration accordingly.

BUG=b:75306520
BRANCH=None
TEST=None

Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b
Signed-off-by: Justin TerAvest 
---
M src/mainboard/google/octopus/variants/baseboard/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/25538/1

diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c
index 3d5d925..8fe1205 100644
--- a/src/mainboard/google/octopus/variants/baseboard/gpio.c
+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c
@@ -87,7 +87,7 @@
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
    PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */
-	PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
    PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */
@@ -264,7 +264,7 @@
 static const struct pad_config early_gpio_table[] = {
    PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
    /* GSPI0_INT */
-	PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
+	PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
    	DISPUPD), /* H1_PCH_INT_ODL */
    /* GSPI0_CLK */
    PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */