Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Rex-BC Chen, Julius Werner, Arthur Heymans, Jianjun Wang.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )

Change subject: coreboot_tables: Add PCIe info to coreboot table
......................................................................

Patch Set 16:

(2 comments)

Patchset:

PS9:
> I think that ctrl_base == config_base

In QC's term, 'config_base' is 'mmio_base'. See CB:57614.

Let me summarize QC and MTK's need here:

```
- MTK: ctrl_base = 0x112f0000
  - mmio_base (config_base) = ctrl_base + 0x1000
  - ctrl_base + 0x140 (for config space mapping)
- QC: ctrl_base = 0x40000000
  - mmio_base = ctrl_base + 0x100000
  - mmio_size
  - atu_base = ctrl_base + 0x1000
```

I think the main question here is, how much data do we want to pass to payload? To go to extremes we could include all register definitions [1] in sysinfo_t. The other end of the spectrum is to pass minimal data (such as ctrl_base), and leave other offsets (0x1000, 0x140, ...) to be defined in each platform driver in libpayload.

[1] https://review.coreboot.org/c/coreboot/+/57615/52/payloads/libpayload/includ...

File src/commonlib/bsd/include/commonlib/bsd/cb_err.h:

https://review.coreboot.org/c/coreboot/+/63251/comment/faf201d1_cb7966d6 
PS16, Line 18: 	
Add one tab for alignment.