[M] Change in coreboot[master]: vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68424 )

(

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04
......................................................................

vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04

Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04.

Changes include:
- FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD

BUG=b:254374913
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.

Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176
Signed-off-by: Shaik Shahina 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424
Reviewed-by: Reka Norman 
Reviewed-by: Kangheui Won 
Reviewed-by: V Sowmya 
Tested-by: build bot (Jenkins) 
---
M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
1 file changed, 78 insertions(+), 52 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  V Sowmya: Looks good to me, approved
  Kangheui Won: Looks good to me, approved
  Reka Norman: Looks good to me, approved

diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
index 05fffb4..057fce7 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
@@ -815,9 +815,11 @@
 **/
   UINT8                       PchFivrDynPm;

-/** Offset 0x0415 - Reserved
+/** Offset 0x0415 - FIVR VCCST ICCMax Control
+  Enable/Disable FIVR VCCST ICCMax Control.
+  $EN_DIS
 **/
-  UINT8                       Reserved10;
+  UINT8                       PchFivrVccstIccMaxControl;

/** Offset 0x0416 - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 500mA
@@ -844,7 +846,7 @@

/** Offset 0x041D - Reserved
 **/
-  UINT8                       Reserved11[3];
+  UINT8                       Reserved10[3];

/** Offset 0x0420 - Extended BIOS Direct Read Decode Range base
   Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
@@ -858,7 +860,7 @@

/** Offset 0x0428 - Reserved
 **/
-  UINT8                       Reserved12[12];
+  UINT8                       Reserved11[12];

/** Offset 0x0434 - CNVi Configuration
   This option allows for automatic detection of Connectivity Solution. [Auto Detection]
@@ -869,7 +871,7 @@

/** Offset 0x0435 - Reserved
 **/
-  UINT8                       Reserved13;
+  UINT8                       Reserved12;

/** Offset 0x0436 - CNVi BT Core
   Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
@@ -987,7 +989,7 @@

/** Offset 0x0455 - Reserved
 **/
-  UINT8                       Reserved14;
+  UINT8                       Reserved13;

/** Offset 0x0456 - OS Timer
   16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
@@ -1023,7 +1025,7 @@

/** Offset 0x04AF - Reserved
 **/
-  UINT8                       Reserved15;
+  UINT8                       Reserved14;

/** Offset 0x04B0 - PCIE RP Detect Timeout Ms
   The number of milliseconds within 0~65535 in reference code will wait for link to
@@ -1134,7 +1136,7 @@

/** Offset 0x0521 - Reserved
 **/
-  UINT8                       Reserved16[8];
+  UINT8                       Reserved15[8];

/** Offset 0x0529 - Enable VMD controller
   Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
@@ -1193,7 +1195,7 @@

/** Offset 0x058D - Reserved
 **/
-  UINT8                       Reserved17[3];
+  UINT8                       Reserved16[3];

/** Offset 0x0590 - VMD Variable
   VMD Variable Pointer.
@@ -1217,7 +1219,7 @@

/** Offset 0x05A0 - Reserved
 **/
-  UINT8                       Reserved18;
+  UINT8                       Reserved17;

/** Offset 0x05A1 - Enable/Disable PMC-PD Solution
   This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
@@ -1272,7 +1274,7 @@

/** Offset 0x05B1 - Reserved
 **/
-  UINT8                       Reserved19;
+  UINT8                       Reserved18;

/** Offset 0x05B2 - ITBT DMA LTR
   TCSS DMA1, DMA2 LTR value
@@ -1281,7 +1283,7 @@

/** Offset 0x05B6 - Reserved
 **/
-  UINT8                       Reserved20;
+  UINT8                       Reserved19;

/** Offset 0x05B7 - Enable/Disable PTM
   This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
@@ -1306,7 +1308,7 @@

/** Offset 0x05C7 - Reserved
 **/
-  UINT8                       Reserved21;
+  UINT8                       Reserved20;

/** Offset 0x05C8 - PCIE RP Snoop Latency Override Value
   Latency Tolerance Reporting, Snoop Latency Override Value.
@@ -1358,7 +1360,7 @@

/** Offset 0x05F3 - Reserved
 **/
-  UINT8                       Reserved22;
+  UINT8                       Reserved21;

/** Offset 0x05F4 - Imon slope correction
   PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
@@ -1385,7 +1387,7 @@

/** Offset 0x0612 - Reserved
 **/
-  UINT8                       Reserved23[2];
+  UINT8                       Reserved22[2];

/** Offset 0x0614 - Thermal Design Current time window
   PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
@@ -1434,7 +1436,7 @@

/** Offset 0x063B - Reserved
 **/
-  UINT8                       Reserved24;
+  UINT8                       Reserved23;

/** Offset 0x063C - Thermal Design Current current limit
   PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
@@ -1503,7 +1505,7 @@

/** Offset 0x0687 - Reserved
 **/
-  UINT8                       Reserved25;
+  UINT8                       Reserved24;

/** Offset 0x0688 - CpuBistData
   Pointer CPU BIST Data
@@ -1540,7 +1542,7 @@

/** Offset 0x0693 - Reserved
 **/
-  UINT8                       Reserved26;
+  UINT8                       Reserved25;

/** Offset 0x0694 - VR Voltage Limit
   PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV
@@ -1555,7 +1557,7 @@

/** Offset 0x06A0 - Reserved
 **/
-  UINT8                       Reserved27[7];
+  UINT8                       Reserved26[7];

/** Offset 0x06A7 - VccIn Aux Imon slope correction
   PCODE MMIO Mailbox: VccIn Aux Imon slope correction. <b>0 - Auto</b> Specified in
@@ -1565,7 +1567,7 @@

/** Offset 0x06A8 - Reserved
 **/
-  UINT8                      Reserved28[2];
+  UINT8                      Reserved27[2];

/** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable
   Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b>
@@ -1574,7 +1576,7 @@

/** Offset 0x06AB - Reserved
 **/
-  UINT8                       Reserved29[13];
+  UINT8                       Reserved28[13];

/** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number
   Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
@@ -1597,7 +1599,7 @@

/** Offset 0x06BC - Reserved
 **/
-  UINT8                       Reserved30[2];
+  UINT8                       Reserved29[2];

/** Offset 0x06BE - Min Voltage for C8
   PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
@@ -1631,7 +1633,7 @@

/** Offset 0x06C9 - Reserved
 **/
-  UINT8                       Reserved31;
+  UINT8                       Reserved30;

/** Offset 0x06CA - CPU VR Power Delivery Design
   Used to communicate the power delivery design capability of the board. This value
@@ -1642,7 +1644,7 @@

/** Offset 0x06CB - Reserved
 **/
-  UINT8                       Reserved32[32];
+  UINT8                       Reserved31[32];

/** Offset 0x06EB - Enable Power Optimizer
   Enable DMI Power Optimizer on PCH side.
@@ -1836,7 +1838,7 @@

/** Offset 0x0894 - Reserved
 **/
-  UINT8                       Reserved33;
+  UINT8                       Reserved32;

/** Offset 0x0895 - Touch Host Controller Port 1 Assignment
   Assign THC Port 1
@@ -1846,7 +1848,7 @@

/** Offset 0x0896 - Reserved
 **/
-  UINT8                      Reserved34[2];
+  UINT8                      Reserved33[2];

/** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux
   Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
@@ -1856,7 +1858,7 @@

/** Offset 0x089C - Reserved
 **/
-  UINT8                       Reserved35;
+  UINT8                       Reserved34;

/** Offset 0x089D - PCIE RP Pcie Speed
   Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
@@ -1888,7 +1890,7 @@

/** Offset 0x0929 - Reserved
 **/
-  UINT8                       Reserved36[28];
+  UINT8                       Reserved35[28];

/** Offset 0x0945 - PCIE RP Ltr Enable
   Latency Tolerance Reporting Mechanism.
@@ -1946,7 +1948,7 @@

/** Offset 0x09A1 - Reserved
 **/
-  UINT8                       Reserved37[3];
+  UINT8                       Reserved36[3];

/** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset
   Allows to select the downstream port preset value that will be used during phase
@@ -2235,7 +2237,7 @@

/** Offset 0x0A45 - Reserved
 **/
-  UINT8                       Reserved38;
+  UINT8                       Reserved37;

/** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value
   Custimized T0Level value.
@@ -2410,7 +2412,7 @@

/** Offset 0x0A6B - Reserved
 **/
-  UINT8                       Reserved39;
+  UINT8                       Reserved38;

/** Offset 0x0A6C - Thermal Device Temperature
   Decides the temperature.
@@ -2435,7 +2437,7 @@

/** Offset 0x0A89 - Reserved
 **/
-  UINT8                       Reserved40[3];
+  UINT8                       Reserved39[3];

/** Offset 0x0A8C - xHCI High Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
@@ -2485,7 +2487,7 @@

/** Offset 0x0A9C - Reserved
 **/
-  UINT8                       Reserved41[4];
+  UINT8                       Reserved40[4];

/** Offset 0x0AA0 - BgpdtHash[4]
   BgpdtHash values
@@ -2499,7 +2501,7 @@

/** Offset 0x0AC4 - Reserved
 **/
-  UINT8                       Reserved42[4];
+  UINT8                       Reserved41[4];

/** Offset 0x0AC8 - BiosGuardModulePtr
   BiosGuardModulePtr default values
@@ -2532,7 +2534,7 @@

/** Offset 0x0ADB - Reserved
 **/
-  UINT8                       Reserved43;
+  UINT8                       Reserved42;

/** Offset 0x0ADC - Change Default SVID
   Change the default SVID used in FSP to programming internal devices. This is only
@@ -2632,7 +2634,7 @@

/** Offset 0x0B00 - Reserved
 **/
-  UINT8                       Reserved44[12];
+  UINT8                       Reserved43[12];

/** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm
   CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
@@ -2725,7 +2727,7 @@

/** Offset 0x0BD1 - Reserved
 **/
-  UINT8                       Reserved45[3];
+  UINT8                       Reserved44[3];

/** Offset 0x0BD4 - CPU PCIE device override table pointer
   The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -3002,7 +3004,7 @@

/** Offset 0x0CA2 - Reserved
 **/
-  UINT8                       Reserved46[2];
+  UINT8                       Reserved45[2];

/** Offset 0x0CA4 - LogoPixelHeight Address
   Address of LogoPixelHeight
@@ -3016,7 +3018,7 @@

/** Offset 0x0CAC - Reserved
 **/
-  UINT8                       Reserved47[5];
+  UINT8                       Reserved46[5];

/** Offset 0x0CB1 - RSR feature
   Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
@@ -3026,7 +3028,7 @@

/** Offset 0x0CB2 - Reserved
 **/
-  UINT8                       Reserved48[4];
+  UINT8                       Reserved47[4];

/** Offset 0x0CB6 - Enable or Disable HWP
   Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
@@ -3419,7 +3421,7 @@

/** Offset 0x0D2D - Reserved
 **/
-  UINT8                       Reserved49;
+  UINT8                       Reserved48;

/** Offset 0x0D2E - Platform Power Pmax
   PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
@@ -3459,7 +3461,7 @@

/** Offset 0x0D3A - Reserved
 **/
-  UINT8                       Reserved50[2];
+  UINT8                       Reserved49[2];

/** Offset 0x0D3C - Package Long duration turbo mode power limit
   Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -3562,7 +3564,7 @@

/** Offset 0x0D73 - Reserved
 **/
-  UINT8                       Reserved51[4];
+  UINT8                       Reserved50[4];

/** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0
   Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
@@ -3634,7 +3636,7 @@

/** Offset 0x0D82 - Reserved
 **/
-  UINT8                       Reserved52;
+  UINT8                       Reserved51;

/** Offset 0x0D83 - Dual Tau Boost
   Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0:
@@ -3645,7 +3647,7 @@

/** Offset 0x0D84 - Reserved
 **/
-  UINT8                       Reserved53[32];
+  UINT8                       Reserved52[32];

/** Offset 0x0DA4 - End of Post message
   Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
@@ -3694,7 +3696,7 @@

/** Offset 0x0DAB - Reserved
 **/
-  UINT8                       Reserved54;
+  UINT8                       Reserved53;

/** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency
   Latency Tolerance Reporting, Max Snoop Latency.
@@ -3846,7 +3848,7 @@

/** Offset 0x0F96 - Reserved
 **/
-  UINT8                       Reserved55[16];
+  UINT8                       Reserved54[16];

/** Offset 0x0FA6 - FOMS Control Policy
   Choose the Foms Control Policy, <b>Default = 0 </b>
@@ -3868,7 +3870,7 @@

/** Offset 0x0FAF - Reserved
 **/
-  UINT8                       Reserved56[33];
+  UINT8                       Reserved55[33];

/** Offset 0x0FD0 - FspEventHandler
   <b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
@@ -3895,7 +3897,7 @@

/** Offset 0x0FD7 - Reserved
 **/
-  UINT8                       Reserved57;
+  UINT8                       Reserved56;

/** Offset 0x0FD8 - Emmc Tx CMD Delay control register value
   Please see Tx CMD Delay Control register definition for help
@@ -3929,7 +3931,7 @@

/** Offset 0x0FF0 - Reserved
 **/
-  UINT8                      Reserved58[69];
+  UINT8                      Reserved57[69];

/** Offset 0x1035 - Enable VMD Global Mapping
   Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
@@ -3939,7 +3941,7 @@

/** Offset 0x1036 - Reserved
 **/
-  UINT8                       Reserved59[138];
+  UINT8                       Reserved58[138];
 } FSP_S_CONFIG;

/** Fsp S UPD Configuration
@@ -3960,7 +3962,7 @@

/** Offset 0x10C0
 **/
-  UINT8                       UnusedUpdSpace45[6];
+  UINT8                       UnusedUpdSpace44[6];

/** Offset 0x10C6
 **/