Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46922 )
Change subject: cpu/intel/haswell: Set C9/C10 vccmin ......................................................................
cpu/intel/haswell: Set C9/C10 vccmin
Backport commit ab7586f ( broadwell: Set C9/C10 vccmin) to Haswell.
Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/registers/mchbar.h 2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46922/1
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 7edb663..1920350 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -247,6 +247,26 @@ return MCHBAR32(BIOS_MAILBOX_DATA); }
+static int pcode_mailbox_write(u32 command, u32 data) +{ + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return -1; + } + + MCHBAR32(BIOS_MAILBOX_DATA) = data; + + /* Send command and start transaction */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return -1; + } + + return 0; +} + static void initialize_vr_config(void) { struct cpu_vr_config vr_config = { 0 }; @@ -321,6 +341,9 @@ else msr.lo |= 0x006f; /* 1.60V */ wrmsr(MSR_VR_MISC_CONFIG2, msr); + + /* Set C9/C10 VCC Min */ + pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); }
static void configure_pch_power_sharing(void) diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 4bdb49a..a61036a 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -46,6 +46,9 @@ #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 +#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 + /* Errors are returned back in bits 7:0 */ #define MAILBOX_BIOS_ERROR_NONE 0 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46922
to look at the new patch set (#6).
Change subject: cpu/intel/haswell: Set C9/C10 vccmin ......................................................................
cpu/intel/haswell: Set C9/C10 vccmin
Backport commit ab7586f ( broadwell: Set C9/C10 vccmin) to Haswell.
Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/registers/mchbar.h 2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46922/6
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46922
to look at the new patch set (#11).
Change subject: cpu/intel/haswell: Set C9/C10 vccmin ......................................................................
cpu/intel/haswell: Set C9/C10 vccmin
Backport commit ab7586fa26 (broadwell: Set C9/C10 vccmin) to Haswell.
Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/registers/mchbar.h 2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46922/11
Attention is currently required from: Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46922 )
Change subject: cpu/intel/haswell: Set C9/C10 vccmin ......................................................................
Patch Set 15: Code-Review+2
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46922 )
Change subject: cpu/intel/haswell: Set C9/C10 vccmin ......................................................................
Patch Set 15: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46922 )
Change subject: cpu/intel/haswell: Set C9/C10 vccmin ......................................................................
cpu/intel/haswell: Set C9/C10 vccmin
Backport commit ab7586fa26 (broadwell: Set C9/C10 vccmin) to Haswell.
Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46922 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/registers/mchbar.h 2 files changed, 26 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index b1f8bba..04f5802 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -226,6 +226,26 @@ return MCHBAR32(BIOS_MAILBOX_DATA); }
+static int pcode_mailbox_write(u32 command, u32 data) +{ + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return -1; + } + + MCHBAR32(BIOS_MAILBOX_DATA) = data; + + /* Send command and start transaction */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return -1; + } + + return 0; +} + static void initialize_vr_config(void) { struct cpu_vr_config vr_config = { 0 }; @@ -300,6 +320,9 @@ else msr.lo |= 0x006f; /* 1.60V */ wrmsr(MSR_VR_MISC_CONFIG2, msr); + + /* Set C9/C10 VCC Min */ + pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); }
static void configure_pch_power_sharing(void) diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 4bdb49a..a61036a 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -46,6 +46,9 @@ #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 +#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 + /* Errors are returned back in bits 7:0 */ #define MAILBOX_BIOS_ERROR_NONE 0 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Michael Niewöhner (Code Review)