Change in coreboot[master]: soc/amd/picasso: Convert BERT reserved region from cbmem

[Marshall Dawson (Code Review)]

Hello Raul Rangel, Felix Held,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/42530

to review the following change.

Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem
......................................................................

soc/amd/picasso: Convert BERT reserved region from cbmem

Picasso's BERT region should not have been moved to cbmem in commit
  901cb9c "soc/amd/picasso: Move BERT region to cbmem".  This
causes an error of "APEI: Can not request [] for APEI BERT registers.

FSP has been modified to set aside a requested region size for BERT,
simiar to TSEG.  Remove the cbmem reservation and locate the region
by searching for the HOB.

BUG=b:136987699
TEST=Check that BERT is allocated

Signed-off-by: Marshall Dawson 
Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb
---
M src/soc/amd/picasso/mca.c
M src/soc/amd/picasso/memmap.c
M src/soc/amd/picasso/romstage.c
3 files changed, 21 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/42530/1

diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c
index cea1c51..69363f5 100644
--- a/src/soc/amd/picasso/mca.c
+++ b/src/soc/amd/picasso/mca.c
@@ -193,31 +193,3 @@
    for (i = 0 ; i < num_banks ; i++)
    	wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts);
 }
-
-void bert_reserved_region(void **start, size_t *size)
-{
-	const struct cbmem_entry *bert;
-
-	*start = NULL;
-	*size = 0;
-
-	bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA);
-	if (!bert)
-		return;
-
-	*start = cbmem_entry_start(bert);
-	*size = cbmem_entry_size(bert);
-}
-
-static void alloc_bert_in_cbmem(int unused)
-{
-	void *p;
-
-	if (CONFIG(ACPI_BERT)) {
-		p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, CONFIG_ACPI_BERT_SIZE);
-		if (!p)
-			printk(BIOS_ERR, "Error: BERT region was not added\n");
-	}
-}
-
-ROMSTAGE_CBMEM_INIT_HOOK(alloc_bert_in_cbmem)
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 42a3307..74a6c70 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -8,6 +8,7 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
+#include <arch/bert_storage.h>
 #include <memrange.h>
 #include <fsp/util.h>
 #include <FspGuids.h>
@@ -60,6 +61,25 @@
    }
 }

+void bert_reserved_region(void **start, size_t *size)
+{
+	struct range_entry bert;
+	int status;
+
+	*start = NULL;
+	*size = 0;
+
+	status = fsp_find_range_hob(&bert, AMD_FSP_BERT_HOB_GUID.b);
+
+	if (status < 0) {
+		printk(BIOS_ERR, "Error: unable to find BERT HOB\n");
+		return;
+	}
+
+	*start = (void *)(uintptr_t)range_entry_base(&bert);
+	*size = range_entry_size(&bert);
+}
+
 void memmap_stash_early_dram_usage(void)
 {
    struct memmap_early_dram *e;
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 83243d3..60a1b04 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -32,6 +32,7 @@

mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
    mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
+	mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
    mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
    mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
    mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42530 )

Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem
......................................................................

Patch Set 1: Code-Review+2

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42530 )

Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem
......................................................................

Patch Set 1:

Where is AGESA allocating said region if all we pass in is the size?

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42530 )

Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42530/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42530/1//COMMIT_MSG@11 
PS1, Line 11: APEI: Can not request [] for APEI BERT registers
Is this the exact error message? I don't see it in the kernel code: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...

Looking at the code, I'm not sure why it can't be in cbmem...

Could it be conflicting with the coreboot driver?

https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42530 )

Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem
......................................................................

Patch Set 1:
> Patch Set 1:
>
> Where is AGESA allocating said region if all we pass in is the size?

See https://chrome-internal-review.googlesource.com/c/chromeos/third_party/amd-f....  It's immediately below TSEG and the TOLUM HOB reported back to coreboot is adjusted downward to accommodate the request.

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42530 )

Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42530/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42530/1//COMMIT_MSG@11 
PS1, Line 11: APEI: Can not request [] for APEI BERT registers
> Is this the exact error message? I don't see it in the kernel code: https://source.chromium. […]

discussion on https://review.coreboot.org/c/coreboot/+/38694 after it got merged has some info on this

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42530 )

Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42530/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42530/1//COMMIT_MSG@11 
PS1, Line 11: APEI: Can not request [] for APEI BERT registers
> Is this the exact error message? I don't see it in the kernel code:
> Could it be conflicting with the coreboot driver?

I think very likely.  And that looks like a pretty good theory.

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42530 )

Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42530/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42530/1//COMMIT_MSG@11 
PS1, Line 11: APEI: Can not request [] for APEI BERT registers
> > Is this the exact error message? I don't see it in the kernel code: […]

Ack

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42530 )

Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem
......................................................................

soc/amd/picasso: Convert BERT reserved region from cbmem

Picasso's BERT region should not have been moved to cbmem in commit
  901cb9c "soc/amd/picasso: Move BERT region to cbmem".  This
causes an error of "APEI: Can not request [] for APEI BERT registers.

FSP has been modified to set aside a requested region size for BERT,
simiar to TSEG.  Remove the cbmem reservation and locate the region
by searching for the HOB.

BUG=b:136987699
TEST=Check that BERT is allocated

Signed-off-by: Marshall Dawson 
Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42530
Reviewed-by: Aaron Durbin 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/picasso/mca.c
M src/soc/amd/picasso/memmap.c
M src/soc/amd/picasso/romstage.c
3 files changed, 21 insertions(+), 28 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved

diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c
index cea1c51..69363f5 100644
--- a/src/soc/amd/picasso/mca.c
+++ b/src/soc/amd/picasso/mca.c
@@ -193,31 +193,3 @@
    for (i = 0 ; i < num_banks ; i++)
    	wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts);
 }
-
-void bert_reserved_region(void **start, size_t *size)
-{
-	const struct cbmem_entry *bert;
-
-	*start = NULL;
-	*size = 0;
-
-	bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA);
-	if (!bert)
-		return;
-
-	*start = cbmem_entry_start(bert);
-	*size = cbmem_entry_size(bert);
-}
-
-static void alloc_bert_in_cbmem(int unused)
-{
-	void *p;
-
-	if (CONFIG(ACPI_BERT)) {
-		p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, CONFIG_ACPI_BERT_SIZE);
-		if (!p)
-			printk(BIOS_ERR, "Error: BERT region was not added\n");
-	}
-}
-
-ROMSTAGE_CBMEM_INIT_HOOK(alloc_bert_in_cbmem)
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 42a3307..74a6c70 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -8,6 +8,7 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
+#include <arch/bert_storage.h>
 #include <memrange.h>
 #include <fsp/util.h>
 #include <FspGuids.h>
@@ -60,6 +61,25 @@
    }
 }

+void bert_reserved_region(void **start, size_t *size)
+{
+	struct range_entry bert;
+	int status;
+
+	*start = NULL;
+	*size = 0;
+
+	status = fsp_find_range_hob(&bert, AMD_FSP_BERT_HOB_GUID.b);
+
+	if (status < 0) {
+		printk(BIOS_ERR, "Error: unable to find BERT HOB\n");
+		return;
+	}
+
+	*start = (void *)(uintptr_t)range_entry_base(&bert);
+	*size = range_entry_size(&bert);
+}
+
 void memmap_stash_early_dram_usage(void)
 {
    struct memmap_early_dram *e;
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index ce8ab5d..7d086fe 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -32,6 +32,7 @@

mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
    mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
+	mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
    mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
    mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
    mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;