Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82995?usp=email )
Change subject: ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h ......................................................................
ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h
Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is: d0771e49e7 MKBP: Increase key matrix size The original include/ec_cmd_api.h version in the EC repo is: d0771e49e7 MKBP: Increase key matrix size
Change-Id: I4f3dfc3f145e50e6114894352cdc118ad5a9565b Signed-off-by: Aseda Aboagye aaboagye@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/82995 Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Forest Mittelberg bmbm@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/ec/google/chromeec/ec_cmd_api.h M src/ec/google/chromeec/ec_commands.h 2 files changed, 165 insertions(+), 1 deletion(-)
Approvals: Caveh Jalali: Looks good to me, approved Forest Mittelberg: Looks good to me, but someone else must approve build bot (Jenkins): Verified
diff --git a/src/ec/google/chromeec/ec_cmd_api.h b/src/ec/google/chromeec/ec_cmd_api.h index 453f507..cab69b7 100644 --- a/src/ec/google/chromeec/ec_cmd_api.h +++ b/src/ec/google/chromeec/ec_cmd_api.h @@ -237,6 +237,12 @@ #define _CROS_EC_C1_F_RF(_cmd, _fn) _CROS_EC_CV_F_R(_cmd, 1, _fn##_v1, _fn##_v1)
/* + * Shorthand for host command version 3 where response name is derived + * from the function name and there is no param. + */ +#define _CROS_EC_C3_F_RF(_cmd, _fn) _CROS_EC_CV_F_R(_cmd, 3, _fn##_v3, _fn##_v3) + +/* * Shorthand for host command version 0 where response and there are no * params or response. */ @@ -312,6 +318,7 @@ _CROS_EC_CV_F_R(EC_CMD_GET_KEYBD_CONFIG, 0, get_keybd_config, keybd_config); _CROS_EC_C0_F_RF(EC_CMD_GET_NEXT_EVENT, get_next_event); _CROS_EC_C1_F_RF(EC_CMD_GET_NEXT_EVENT, get_next_event); +_CROS_EC_C3_F_RF(EC_CMD_GET_NEXT_EVENT, get_next_event); _CROS_EC_CV_F_R(EC_CMD_GET_NEXT_EVENT, 2, get_next_event_v2, get_next_event_v1); _CROS_EC_C0_F_PF_RF(EC_CMD_GET_PD_PORT_CAPS, get_pd_port_caps); _CROS_EC_C0_F_RF(EC_CMD_GET_PROTOCOL_INFO, get_protocol_info); @@ -368,6 +375,8 @@ _CROS_EC_C0_F_RF(EC_CMD_PCHG_COUNT, pchg_count); _CROS_EC_CV_F_P(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, pd_charge_port_override, charge_port_override); +_CROS_EC_CV_F_P_R(EC_CMD_PD_CHIP_INFO, 2, pd_chip_info_v2, pd_chip_info, + pd_chip_info_v2); _CROS_EC_CV_F_P_R(EC_CMD_PD_CHIP_INFO, 1, pd_chip_info_v1, pd_chip_info, pd_chip_info_v1); _CROS_EC_C0_F_PF_RF(EC_CMD_PD_CHIP_INFO, pd_chip_info); @@ -403,6 +412,7 @@ _CROS_EC_C0_F_PF(EC_CMD_RWSIG_ACTION, rwsig_action); _CROS_EC_C0_F_RF(EC_CMD_RWSIG_CHECK_STATUS, rwsig_check_status); _CROS_EC_C0_F_RF(EC_CMD_RWSIG_INFO, rwsig_info); +_CROS_EC_C0_F_PF(EC_CMD_SET_ALARM_SLP_S0_DBG, set_alarm_slp_s0_dbg); _CROS_EC_C0_F_PF(EC_CMD_SET_BASE_STATE, set_base_state); _CROS_EC_C0_F_PF(EC_CMD_SET_TABLET_MODE, set_tablet_mode); _CROS_EC_C0_F_PF_RF(EC_CMD_SMART_DISCHARGE, smart_discharge); diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index f57b699c..1673c8b 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -3970,6 +3970,11 @@ * Get the next pending MKBP event. * * Returns EC_RES_UNAVAILABLE if there is no event pending. + * + * V0: ec_response_get_next_data + * V1: ec_response_get_next_data_v1. Increased key_matrix size from 13 -> 16. + * V2: Added EC_MKBP_HAS_MORE_EVENTS. + * V3: ec_response_get_next_data_v3. Increased key_matrix size from 16 -> 18. */ #define EC_CMD_GET_NEXT_EVENT 0x0067
@@ -4107,6 +4112,34 @@ }; BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16);
+union __ec_align_offset1 ec_response_get_next_data_v3 { + uint8_t key_matrix[18]; + + /* Unaligned */ + uint32_t host_event; + uint64_t host_event64; + + struct __ec_todo_unpacked { + /* For aligning the fifo_info */ + uint8_t reserved[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; + + uint32_t buttons; + + uint32_t switches; + + uint32_t fp_events; + + uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; + + uint8_t cec_message[16]; +}; +BUILD_ASSERT(sizeof(union ec_response_get_next_data_v3) == 18); + struct ec_response_get_next_event { uint8_t event_type; /* Followed by event data if any */ @@ -4119,6 +4152,12 @@ union ec_response_get_next_data_v1 data; } __ec_align1;
+struct ec_response_get_next_event_v3 { + uint8_t event_type; + /* Followed by event data if any */ + union ec_response_get_next_data_v3 data; +} __ec_align1; + /* Bit indices for buttons and switches.*/ /* Buttons */ #define EC_MKBP_POWER_BUTTON 0 @@ -4587,6 +4626,9 @@ uint8_t subcmd; /* enum ec_console_read_subcmd */ } __ec_align1;
+/* Print directly to EC console from host. */ +#define EC_CMD_CONSOLE_PRINT 0x00AC + /*****************************************************************************/
/* @@ -5818,6 +5860,7 @@ #define PD_EVENT_IDENTITY_RECEIVED BIT(2) #define PD_EVENT_DATA_SWAP BIT(3) #define PD_EVENT_TYPEC BIT(4) +#define PD_EVENT_PPM BIT(5)
struct ec_response_host_event_status { uint32_t status; /* PD MCU host event status */ @@ -6289,6 +6332,37 @@ } __ec_align2; } __ec_align2;
+/** Indicates the chip should NOT receive a firmware update, if set. This is + * useful when multiple ports are serviced by a single chip, to avoid + * performing redundant updates. The host command implementation shall ensure + * only one port out of each physical chip has FW updates active. + */ +#define USB_PD_CHIP_INFO_FWUP_FLAG_NO_UPDATE BIT(0) + +/** Maximum length of a project name embedded in a PDC FW image. This length + * does NOT include a NUL-terminator. + */ +#define USB_PD_CHIP_INFO_PROJECT_NAME_LEN 12 +struct ec_response_pd_chip_info_v2 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + } __ec_align2; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + } __ec_align2; + /** Flag to control the FW update process for this chip. */ + uint16_t fw_update_flags; + /** Project name string associated with the chip's FW. Add an extra + * byte for a NUL-terminator. + */ + char fw_name_str[USB_PD_CHIP_INFO_PROJECT_NAME_LEN + 1]; +} __ec_align2; + /* Run RW signature verification and get status */ #define EC_CMD_RWSIG_CHECK_STATUS 0x011C
@@ -6396,6 +6470,38 @@ } __ec_align1;
/* + * Retrieve binary from CrOS Board Info primary memory source. + */ +#define EC_CMD_CBI_BIN_READ 0x0504 +/* + * Write binary into CrOS Board Info temporary buffer and then commit it to + * permanent storage once complete. Write fails if the board has hardware + * write-protect enabled. + */ +#define EC_CMD_CBI_BIN_WRITE 0x0505 + +/* + * CBI binary read/write flags + * The default write behavior is to always append any data to the buffer. + * If 'CLEAR' flag is set, buffer is cleared then data is appended. + * If 'WRITE' flag is set, data is appended then buffer is written to memory. + */ +#define EC_CBI_BIN_BUFFER_CLEAR BIT(0) +#define EC_CBI_BIN_BUFFER_WRITE BIT(1) + +struct ec_params_get_cbi_bin { + uint32_t offset; /* Data offset */ + uint32_t size; /* Data size */ +} __ec_align4; + +struct ec_params_set_cbi_bin { + uint32_t offset; /* Data offset */ + uint32_t size; /* Data size */ + uint8_t flags; /* bit field for EC_CBI_BIN_COMMIT_FLAG_* */ + uint8_t data[]; /* For string and raw data */ +} __ec_align1; + +/* * Information about resets of the AP by the EC and the EC's own uptime. */ #define EC_CMD_GET_UPTIME_INFO 0x0121 @@ -6798,6 +6904,8 @@ TK_MICMUTE = 19, TK_MENU = 20, TK_DICTATE = 21, + TK_ACCESSIBILITY = 22, + TK_DONOTDISTURB = 23,
TK_COUNT }; @@ -7856,6 +7964,36 @@ uint32_t state; } __ec_align1;
+/* + * UCSI OPM-PPM commands + * + * These commands are used for communication between OPM and PPM. + * Only UCSI3.0 is tested. + */ + +#define EC_CMD_UCSI_PPM_SET 0x0140 + +/* The data size is stored in the host command protocol header. */ +struct ec_params_ucsi_ppm_set { + uint16_t offset; + uint8_t data[]; +} __ec_align2; + +#define EC_CMD_UCSI_PPM_GET 0x0141 + +/* For 'GET' sub-commands, data will be returned as a raw payload. */ +struct ec_params_ucsi_ppm_get { + uint16_t offset; + uint8_t size; +} __ec_align2; + +#define EC_CMD_SET_ALARM_SLP_S0_DBG 0x0142 + +/* RTC params and response structures */ +struct ec_params_set_alarm_slp_s0_dbg { + uint32_t time; +} __ec_align2; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */
@@ -8023,7 +8161,8 @@
/* Constants for encryption parameters */ #define FP_CONTEXT_NONCE_BYTES 12 -#define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t)) +#define FP_CONTEXT_USERID_BYTES 32 +#define FP_CONTEXT_USERID_WORDS (FP_CONTEXT_USERID_BYTES / sizeof(uint32_t)) #define FP_CONTEXT_TAG_BYTES 16 #define FP_CONTEXT_ENCRYPTION_SALT_BYTES 16 #define FP_CONTEXT_TPM_BYTES 32 @@ -8255,6 +8394,21 @@ uint16_t fgr_num; } __ec_align4;
+/* + * Migrate a legacy FP template (here, legacy refers to being generated in a + * raw user_id context instead of a nonce context) by wiping its match secret + * salt and treating it as a newly-enrolled template. + * The legacy FP template needs to be uploaded by FP_TEMPLATE command first + * without committing, then this command will commit it. + */ +#define EC_CMD_FP_MIGRATE_TEMPLATE_TO_NONCE_CONTEXT 0x0418 + +struct ec_params_fp_migrate_template_to_nonce_context { + /* The context userid used to encrypt this template when it was created. + */ + uint32_t userid[FP_CONTEXT_USERID_WORDS]; +}; + /*****************************************************************************/ /* Touchpad MCU commands: range 0x0500-0x05FF */
-
Felix Held (Code Review)