[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock

[Werner Zeh (Code Review)]

Attention is currently required from: Lean Sheng Tan.

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68669 )

Change subject: mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock
......................................................................

mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock

After some measurements it turned out that Elkhart Lake uses a higher
CSR clock internally from which the MDIO clock is derived. In order to
stay compliant with the specification, the MDIO clock needs to be lower
than 2.5 MHz. Therefore, the divider needs to be 102 and not 62.
This patch changes the define to match the new divider value and uses
this new define at the appropriate place.

Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz.

Change-Id: Idf498c3547530dfa395f54488ef244e787062e34
Signed-off-by: Werner Zeh 
---
M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
M src/soc/intel/elkhartlake/tsn_gbe.c
2 files changed, 22 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/68669/1

diff --git a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
index b1d04cc..cd9f12e 100644
--- a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
+++ b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
@@ -15,7 +15,7 @@
 #define  TSN_MAC_PHYAD(pa)		(pa << 21)	/* Physical Layer Address */
 #define  TSN_MAC_REGAD(rda)		(rda << 16)	/* Register/Device Address */
 #define  TSN_MAC_CLK_TRAIL_4		(4 << 12)	/* 4 Trailing Clocks */
-#define  TSN_MAC_CSR_CLK_DIV_62		(1 << 8)	/* 0001: CSR=100-150 MHz; CSR/62 */
+#define  TSN_MAC_CSR_CLK_DIV_102	(1 << 10)	/* 0100: CSR=150-250 MHz; CSR/102 */
 #define  TSN_MAC_OP_CMD_WRITE		(1 << 2)	/* GMII Operation Command Write */
 #define  TSN_MAC_OP_CMD_READ		(3 << 2)	/* GMII Operation Command Read */
 #define  TSN_MAC_GMII_BUSY		(1 << 0)	/* GMII Busy bit */
diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c
index 3e08897..2a1468c 100644
--- a/src/soc/intel/elkhartlake/tsn_gbe.c
+++ b/src/soc/intel/elkhartlake/tsn_gbe.c
@@ -52,7 +52,7 @@

clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK,
    		TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr)
-			| TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62
+			| TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102
    		| TSN_MAC_OP_CMD_READ | TSN_MAC_GMII_BUSY);

/* Wait for MDIO frame transfer to complete before reading MDIO DATA register */
@@ -75,7 +75,7 @@
    write16(base + TSN_MAC_MDIO_DATA, data);
    clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK,
    		TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr)
-			| TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62
+			| TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102
    		| TSN_MAC_OP_CMD_WRITE | TSN_MAC_GMII_BUSY);

/* Wait for MDIO frame transfer to complete before do next */