Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49743 )
Change subject: sb/intel/lynxpoint: Replace HPET_ADDR ......................................................................
sb/intel/lynxpoint: Replace HPET_ADDR
Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/romstage.c M src/southbridge/intel/lynxpoint/pch.h 2 files changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49743/1
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 3227c02..0fa036e 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -55,7 +55,7 @@ .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .hpet_address = HPET_ADDR, + .hpet_address = CONFIG_HPET_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 2833356..d03d91a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -63,8 +63,6 @@ #define DEFAULT_GPIOSIZE 0x80 #endif
-#define HPET_ADDR 0xfed00000 - #include <southbridge/intel/common/rcba.h>
#ifndef __ACPI__