[S] Change in coreboot[master]: soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68252 )

Change subject: soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control
......................................................................

soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control

Enable the VCCST ICCMax Control for the ADL-N display flicker issue.
Please refer the Doc with ID 742988 for more details.

BUG=b:248249033
TEST=Verified that the display flicker issue is fixed.

Signed-off-by: V Sowmya 
Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68252
Reviewed-by: Reka Norman 
Reviewed-by: Baieswara Reddy Sagili 
Tested-by: build bot (Jenkins) 
Reviewed-by: Kangheui Won 
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 30 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kangheui Won: Looks good to me, approved
  Baieswara Reddy Sagili: Looks good to me, but someone else must approve
  Reka Norman: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 5346403..dda2145 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1068,6 +1068,15 @@

s_cfg->PchFivrExtVnnRailIccMaximum =
    		config->ext_fivr_settings.vnn_icc_max_ma;
+
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
+	/* Enable the FIVR VCCST ICCMax Control for ADL-N.
+	 * TODO:Right now the UPD is update in partial headers for only ADL-N and when its
+	 * updated for ADL-P then we will remove the config since this needs to be enabled for
+	 * all the Alderlake platforms.
+	 */
+	s_cfg->PchFivrVccstIccMaxControl = 1;
+#endif
 }

static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,