Change in coreboot[master]: amd/stoneyridge: Add GNB IOAPIC init

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/25541

Change subject: amd/stoneyridge: Add GNB IOAPIC init
......................................................................

amd/stoneyridge: Add GNB IOAPIC init

Use standard coreboot function to set virtual wire mode on
the GNB IOAPIC.

BUG=b:74104946
TEST=Check GNB IOAPIC debug output on serial.

Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0
Signed-off-by: Marc Jones 
---
M src/soc/amd/stoneyridge/northbridge.c
1 file changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25541/1

diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index c640c1f..b725f9e 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -15,6 +15,7 @@

#include <arch/io.h>
+#include <arch/ioapic.h>
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <cbmem.h>
@@ -69,12 +70,20 @@

static void read_resources(device_t dev)
 {
+	struct resource *res;
+
    /*
     * This MMCONF resource must be reserved in the PCI domain.
     * It is not honored by the coreboot resource allocator if it is in
     * the CPU_CLUSTER.
     */
    mmconf_resource(dev, MMIO_CONF_BASE);
+
+	/* NB IOAPIC2  resource */
+	res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */
+	res->base = IO_APIC2_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }

static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
@@ -165,6 +174,7 @@

static void northbridge_init(struct device *dev)
 {
+	setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1);
 }

static unsigned long acpi_fill_hest(acpi_hest_t *hest)