[XS] Change in coreboot[main]: mb/google/rex/var/deku: Enable RTD3 for SSD

[Curtis Chen (Code Review)]

Curtis Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84452?usp=email )

Change subject: mb/google/rex/var/deku: Enable RTD3 for SSD
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mb/google/rex/var/deku: Enable RTD3 for SSD

Deku S0ix is blocked by SSD. Enable RTD3 for SSD to unblock S0ix.

BUG=361011799
TEST=Deku can enter into S0iX.

Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649
Signed-off-by: Curtis Chen 
---
M src/mainboard/google/rex/variants/deku/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/84452/1

diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb
index f51a0cd..3b4dce9 100644
--- a/src/mainboard/google/rex/variants/deku/overridetree.cb
+++ b/src/mainboard/google/rex/variants/deku/overridetree.cb
@@ -167,6 +167,13 @@
    			.clk_req = 7,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
+				register "srcclk_pin" = "7"
+				device generic 0 on end
+			end
    	end	# PCIE11 SSD card
    	device ref tbt_pcie_rp0 on end
    	device ref tbt_pcie_rp1 on end