[S] Change in coreboot[master]: src: Move POST_BOOTBLOCK_CAR to common postcodes and use it

[Elyes Haouas (Code Review)]

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71596 )

Change subject: src: Move POST_BOOTBLOCK_CAR to common postcodes and use it
......................................................................

src: Move POST_BOOTBLOCK_CAR to common postcodes and use it

This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific
postcodes into the common postcode list, and uses it for the
cache-as-RAM init as needed.

Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in
most of the others, the values were consolidated into 0x21.  This will
change the value on some platforms.

Any conflicts should get sorted out later in the conversion process.

Signed-off-by: Martin Roth 
Change-Id: I8527334e679a23006b77a5645f919aea76dd4926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596
Tested-by: build bot (Jenkins) 
Reviewed-by: Elyes Haouas 
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/drivers/intel/fsp1_1/cache_as_ram.S
M src/include/cpu/intel/post_codes.h
M src/soc/intel/common/block/include/intelblocks/post_codes.h
5 files changed, 31 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Elyes Haouas: Looks good to me, approved

diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index ef296bd..a8a8d95 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -72,6 +72,12 @@
 #define POST_ENTRY_C_START			0x13

/**
+ * \brief Entry into bootblock cache-as-RAM code
+ *
+ */
+#define POST_BOOTBLOCK_CAR			0x21
+
+/**
  * \brief Entry into pci_scan_bus
  *
  * Entered pci_scan_bus()
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index f828d6f..617da53 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -15,7 +15,7 @@
 bootblock_pre_c_entry:

cache_as_ram:
-	post_code(0x20)
+	post_code(POST_BOOTBLOCK_CAR)
    /*
     * Nothing to do here on qemu, RAM works just fine without any
     * initialization.
@@ -103,7 +103,6 @@
 #endif

before_c_entry:
-	post_code(0x29)
    call	bootblock_c_entry_bist
    /* Never returns */
 .Lhlt:
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
index 6a19b87..571feb4 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.S
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -34,7 +34,7 @@
    movd	%eax, %mm1

cache_as_ram:
-	post_code(0x20)
+	post_code(POST_BOOTBLOCK_CAR)

/* Cache the rom and update the microcode */
 cache_rom:
@@ -181,8 +181,6 @@
    pushl	%eax	/* tsc[31:0] */

before_romstage:
-	post_code(0x2a)
-
    /* Call bootblock_c_entry(uint64_t base_timestamp) */
    call	bootblock_c_entry

diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h
index 3db0aeb..6c1ca79 100644
--- a/src/include/cpu/intel/post_codes.h
+++ b/src/include/cpu/intel/post_codes.h
@@ -3,7 +3,6 @@
 #ifndef CPU_INTEL_CAR_POST_CODES_H
 #define CPU_INTEL_CAR_POST_CODES_H

-#define POST_BOOTBLOCK_CAR				0x20
 #define POST_SOC_SET_DEF_MTRR_TYPE			0x21
 #define POST_SOC_CLEAR_FIXED_MTRRS			0x22	// Intentional Duplicate
 #define POST_SOC_DETERMINE_CPU_ADDR_BITS		0x22
diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h
index d7c0ef1..7c78ef8 100644
--- a/src/soc/intel/common/block/include/intelblocks/post_codes.h
+++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h
@@ -16,9 +16,6 @@
 #define POST_SOC_CAR_INIT_DONE				0x29
 #define POST_SOC_BEFORE_CARSTAGE			0x2a

-/* common/block/cpu/car/cache_as_ram_fsp.S */
-#define POST_BOOTBLOCK_CAR				0x21
-
 /* common/block/cse/cse.c */
 #define POST_CODE_ZERO					0x00
 #endif