[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO high range

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Nico Huber has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83538?usp=email )

Change subject: soc/intel/xeon_sp: Reserve MMIO high range
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Patch Set 4:

(1 comment)

Patchset:

PS2:
> Emm, I need some time to do some thinking around your inputs. Nico, may I have an example of coreboot allocated domain resource window?

Examples are probably in coreboot's past, e.g. HyperTransport support.
Might not be worth to look into, though, as the code wasn't the best. It
generally depends on the order of things in coreboot's execution sequence.
If you only need it late, for instance, I see no problem in treating these things
like any other bridge window (i.e. having only a single resource domain).
OTOH, if you need it earlier, there would have to be some additional code.
Though, once those "domains" are in the devicetree, expressed in coreboot's
structures, there wouldn't be anything in the way to write common code
(e.g. a simple loop over all domains that partitions the available space).
> BTW, should we merge this change in parallel while continuing the discussion?

Sure. If I mark something as resolved (and write "Side note" or such), I
really don't mean to hold anything back.

Somebody with more insight into FSP should probably ack this patch, though.