Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57782 )
Change subject: soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init ......................................................................
soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region, we need to call enable_acpimmio_decode_pm04 here first so that accessing the GPIO registers will work.
BUG=None TEST=Build and boot to OS in Guybrush.
Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473 Signed-off-by: Felix Held felix-coreboot@felixheld.de Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/picasso/early_fch.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 9 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index bddcbee..7782d43 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -44,9 +44,11 @@ /* Before console init */ void fch_pre_init(void) { + /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access + the GPIO registers. */ + enable_acpimmio_decode_pm04(); lpc_early_init(); fch_spi_early_init(); - enable_acpimmio_decode_pm04(); fch_smbus_init(); fch_enable_cf9_io(); fch_enable_legacy_io(); diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index ae3aed2..3d1cd1b 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -42,13 +42,15 @@ /* Before console init */ void fch_pre_init(void) { + /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access + the GPIO registers. */ + enable_acpimmio_decode_pm04(); lpc_early_init();
if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) lpc_configure_decodes();
fch_spi_early_init(); - enable_acpimmio_decode_pm04(); fch_smbus_init(); fch_enable_cf9_io(); fch_enable_legacy_io(); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7493770..de27ac5 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -328,6 +328,9 @@ { int reboot = 0;
+ /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access + the GPIO registers. */ + enable_acpimmio_decode_pm04(); lpc_enable_rom(); sb_enable_lpc(); lpc_enable_port80(); @@ -335,7 +338,6 @@ lpc_enable_spi_prefetch(); sb_init_spi_base(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ - enable_acpimmio_decode_pm04(); fch_smbus_init(); fch_enable_cf9_io(); setup_spread_spectrum(&reboot);