PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29859
Change subject: Documentation/../../kblrvp11: Add RVP11 documentation ......................................................................
Documentation/../../kblrvp11: Add RVP11 documentation
Signed-off-by: Praveen hodagatta pranesh praveenx.hodagatta.pranesh@intel.com Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd --- M Documentation/mainboard/index.md A Documentation/mainboard/intel/kblrvp11.md 2 files changed, 68 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29859/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 128f0c1..62fd276 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -24,6 +24,7 @@
- [DG43GT](intel/dg43gt.md) - [IceLake RVP](intel/icelake_rvp.md) +- [KBLRVP11](intel/kblrvp11.md)
## Foxconn
diff --git a/Documentation/mainboard/intel/kblrvp11.md b/Documentation/mainboard/intel/kblrvp11.md new file mode 100644 index 0000000..674f5e2 --- /dev/null +++ b/Documentation/mainboard/intel/kblrvp11.md @@ -0,0 +1,67 @@ +# Intel Kaby lake RVP11 + +## Specs + +* 1 SATA cable connect +* 1 SATAe direct +* 2 USB2.0 connector +* 4 USB3.0 connector +* 1 Gigabit Ethernet +* 1 x4 PCIe slot +* 1 x1 PCIe slot +* 1 X16 PEG slot +* UART debug DB9 connector +* 4 DIMMS with DDR4 memory +* SPI flash +* Audio Jack +* PS2 Keyboard and Mouse +* Display: HDMI, DP, VGA + +## Target Audience + +* OEMs, internal only + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q128FV | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | No | ++---------------------+------------+ +``` + +### Instruction to flash coreboot to SPI + +1. Dediprog SF600 with adapter B is used. +2. Make sure power supply is disconnected from board. +3. Connect Dediprog SF600 to header at J7H1. +4. Ensure that "currently working on" is in "application memory chip 1" +5. Go to "file" and select the .rom file (16 MB) to program chip1. +6. Execute the batch operation to erase and program the chip. + +## Technology + +```eval_rst ++------------------+---------------------------------------------------+ +| CPU | Kaby lake H (i7-7820EQ) | ++------------------+---------------------------------------------------+ +| PCH | Skylake PCH-H (called SPT-H) | ++------------------+---------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+---------------------------------------------------+ +``` + +[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pd...
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PraveenX Hodagatta Pranesh (Code Review)