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Elyes Haouas has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
Patch Set 78:
(3 comments)
File src/soc/intel/pantherlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/5479d079_8c0d9e87?usp... :
PS78, Line 7: stddef.h>
not sure if this is used here
File src/soc/intel/pantherlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/83635/comment/ca8fb129_037094c2?usp... :
PS78, Line 3: console/console.h>
not sure if this is used
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83635/comment/dd65d624_2a12c5a0?usp... :
PS78, Line 3: #include <assert.h>
: #include <console/console.h>
: #include <cpu/intel/cpu_ids.h>
: #include <cpu/x86/msr.h>
: #include <cpu/intel/common/common.h>
: #include <device/device.h>
: #include <drivers/wifi/generic/wifi.h>
: #include <fsp/fsp_debug_event.h>
: #include <fsp/util.h>
: #include <intelblocks/cpulib.h>
: #include <intelblocks/pcie_rp.h>
: #include <option.h>
: #include <soc/iomap.h>
: #include <soc/msr.h>
: #include <soc/pci_devs.h>
: #include <soc/pcie.h>
: #include <soc/romstage.h>
: #include <soc/soc_chip.h>
: #include <soc/soc_info.h>
: #include <string.h>
are you using all of those files?
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