Change in coreboot[master]: soc/intel/xeon_sp/cpx: Fix bootblock size with CBnT

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50082 )

Change subject: soc/intel/xeon_sp/cpx: Fix bootblock size with CBnT
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soc/intel/xeon_sp/cpx: Fix bootblock size with CBnT

Change-Id: Ic5ad9d29f247b6f828501bfacc27a8af08761d55
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/Kconfig
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/50082/1

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 5f1e9a3..aa9dda4 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -5,6 +5,8 @@
 config SOC_SPECIFIC_OPTIONS
    def_bool y
    select MICROCODE_BLOB_NOT_HOOKED_UP
+	# With CBnT the bootblock is set up as a CBnT IBB and needs a fixed size
+	select FIXED_BOOTBLOCK_SIZE if INTEL_CBNT_SUPPORT

config FSP_HEADER_PATH
      string "Location of FSP headers"
@@ -60,6 +62,13 @@
      allocated at 0xfe800000 (the CAR base) and consumes about 0x130000
      bytes of memory.

+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0xc000 if FIXED_BOOTBLOCK_SIZE
+	help
+	  This matches the IBB size used for CBnT. Adjust this to the
+	  used CBnT settings.
+
 config CPU_MICROCODE_CBFS_LOC
    hex
    default 0xfff0fdc0