Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81927?usp=email )
Change subject: [LNL]: [TEST]Enable MRC Cache R/W for x64 ......................................................................
[LNL]: [TEST]Enable MRC Cache R/W for x64
Change-Id: I68ad6d3a95d51ef205640785804b73fcdc27a830 Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- M src/soc/intel/common/block/fast_spi/fast_spi_flash.c 1 file changed, 24 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/81927/1
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index e9cfc23..f4ad2fe 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -73,12 +73,34 @@ return fast_spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA); }
+static void memcpy2(void* addr, const void* data, size_t len) { + size_t i; + uint32_t *dst32 = (uint32_t*) addr; + const uint32_t *src32 = (const uint32_t*) data; + uint8_t *dst8 = NULL; + const uint8_t *src8 = NULL; + size_t a = len % 4; + size_t b = len / 4; + + // Copy in 32-bit chunks + for (i = 0; i < b; i++) + *dst32++ = *src32++; + + dst8 = (uint8_t*) (dst32); + src8 = (const uint8_t*) (src32); + + // Copy any remaining bytes one by one + for (i = 0; i < a; i++) { + *dst8++ = *src8++; + } +} + /* Fill FDATAn FIFO in preparation for a write transaction. */ static void fill_xfer_fifo(struct fast_spi_flash_ctx *ctx, const void *data, size_t len) { /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); + memcpy2((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); }
/* Drain FDATAn FIFO after a read transaction populates data. */ @@ -86,7 +108,7 @@ size_t len) { /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len); + memcpy2(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len); }
/* Fire up a transfer using the hardware sequencer. */