Change in coreboot[master]: soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59310 )

Change subject: soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT
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soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT

This patch uses `clrsetbits32` helper function to set thermal
device Low Temp Threshold (LTT) value.

BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp with this change.

Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59310
Reviewed-by:  Felix Singer 
Reviewed-by: EricR Lai 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/thermal/thermal.c
1 file changed, 1 insertion(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
   Felix Singer: Looks good to me, but someone else must approve
  EricR Lai: Looks good to me, approved

diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c
index 4a2d8d8..6106c49 100644
--- a/src/soc/intel/common/block/thermal/thermal.c
+++ b/src/soc/intel/common/block/thermal/thermal.c
@@ -40,7 +40,6 @@
 /* Enable thermal sensor power management */
 void pch_thermal_configuration(void)
 {
-	uint16_t reg16;
    uintptr_t thermalbar;
    uintptr_t thermalbar_pm;
    const struct device *dev;
@@ -65,9 +64,5 @@
    thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT;

/* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */
-	reg16 = read16((uint16_t *)thermalbar_pm);
-	reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK;
-	/* Low Temp Threshold (LTT) */
-	reg16 |= pch_get_ltt_value();
-	write16((uint16_t *)thermalbar_pm, reg16);
+	clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value());
 }

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.