[S] Change in coreboot[master]: mb/google/rex: Set FVM configuration for MTL-P 28W

[Subrata Banik (Code Review)]

Attention is currently required from: Kapil Porwal, Tarun Tuli.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75764?usp=email )

Change subject: mb/google/rex: Set FVM configuration for MTL-P 28W
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mb/google/rex: Set FVM configuration for MTL-P 28W

This patch sets the FVM configuration parameter as suggested in Intel
doc 640982. As per the doc, Intel MTL-P 28W CPU supports FVM on IA, GT
and SA.

The baseline Icc max for IA is 93A, 53A for GT and 35A for SA.

BUG=b:286809233
TEST=Able to build and boot google/rex without seeing any performance
regression.

Change-Id: If834c1af8141a19fd2daae653579225b77cfa6c8
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/75764/1

diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
index 9a71e95..d776450 100644
--- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
@@ -53,6 +53,21 @@
    register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
    register "pch_hda_idisp_codec_enable" = "1"

+	# As per doc 640982, Intel MTL-P 28W CPU supports FVM on IA, GT and SA
+	# The ICC Limit is represented in 1/4 A increments, i.e., A value of 400 = 100A
+	# For IA VR configuration
+	register "enable_fast_vmode[VR_DOMAIN_IA]" = "1"
+	register "cep_enable[VR_DOMAIN_IA]" = "1"
+	register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "372" # 93A
+	# For GT VR configuration
+	register "enable_fast_vmode[VR_DOMAIN_GT]" = "1"
+	register "cep_enable[VR_DOMAIN_GT]" = "1"
+	register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "212" # 53A
+	# For SA VR configuration
+	register "enable_fast_vmode[VR_DOMAIN_SA]" = "1"
+	register "cep_enable[VR_DOMAIN_SA]" = "1"
+	register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "140" # 35A
+
    device domain 0 on
    	device ref igpu on end
    	device ref dtt on end