Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56256 )
Change subject: src/soc/intel/*: Change legacy_8254_timer to CMOS option ......................................................................
src/soc/intel/*: Change legacy_8254_timer to CMOS option
Change legacy_8254_timer to be CMOS option rather than Kconfig to allow it to be changed at runtime.
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 --- M src/mainboard/hp/280_g2/Kconfig A src/mainboard/hp/280_g2/cmos.default A src/mainboard/hp/280_g2/cmos.layout M src/mainboard/purism/librem_cnl/Kconfig A src/mainboard/purism/librem_cnl/cmos.default A src/mainboard/purism/librem_cnl/cmos.layout M src/mainboard/system76/lemp9/Kconfig A src/mainboard/system76/lemp9/cmos.default A src/mainboard/system76/lemp9/cmos.layout M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/timer/Kconfig M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 17 files changed, 130 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/56256/1
diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig index 10f6828..8102d66 100644 --- a/src/mainboard/hp/280_g2/Kconfig +++ b/src/mainboard/hp/280_g2/Kconfig @@ -36,7 +36,4 @@ int default 2
-config USE_LEGACY_8254_TIMER - default y - endif diff --git a/src/mainboard/hp/280_g2/cmos.default b/src/mainboard/hp/280_g2/cmos.default new file mode 100644 index 0000000..cde52aa --- /dev/null +++ b/src/mainboard/hp/280_g2/cmos.default @@ -0,0 +1 @@ +legacy_8254_timer=Disable diff --git a/src/mainboard/hp/280_g2/cmos.layout b/src/mainboard/hp/280_g2/cmos.layout new file mode 100644 index 0000000..3012f30 --- /dev/null +++ b/src/mainboard/hp/280_g2/cmos.layout @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: Devices +453 1 e 1 legacy_8254_timer + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +# ----------------------------------------------------------------- +checksums + +checksum 392 453 984 diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 5763a19..8723bee 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -11,7 +11,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_CACHE_IN_FMAP select SPD_READ_BY_WORD - select USE_LEGACY_8254_TIMER
if BOARD_PURISM_BASEBOARD_LIBREM_CNL
diff --git a/src/mainboard/purism/librem_cnl/cmos.default b/src/mainboard/purism/librem_cnl/cmos.default new file mode 100644 index 0000000..cde52aa --- /dev/null +++ b/src/mainboard/purism/librem_cnl/cmos.default @@ -0,0 +1 @@ +legacy_8254_timer=Disable diff --git a/src/mainboard/purism/librem_cnl/cmos.layout b/src/mainboard/purism/librem_cnl/cmos.layout new file mode 100644 index 0000000..3012f30 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/cmos.layout @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: Devices +453 1 e 1 legacy_8254_timer + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +# ----------------------------------------------------------------- +checksums + +checksum 392 453 984 diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index 675b738..9bef81a 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -19,7 +19,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP - select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
config MAINBOARD_DIR string diff --git a/src/mainboard/system76/lemp9/cmos.default b/src/mainboard/system76/lemp9/cmos.default new file mode 100644 index 0000000..cde52aa --- /dev/null +++ b/src/mainboard/system76/lemp9/cmos.default @@ -0,0 +1 @@ +legacy_8254_timer=Disable diff --git a/src/mainboard/system76/lemp9/cmos.layout b/src/mainboard/system76/lemp9/cmos.layout new file mode 100644 index 0000000..3012f30 --- /dev/null +++ b/src/mainboard/system76/lemp9/cmos.layout @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: Devices +453 1 e 1 legacy_8254_timer + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +# ----------------------------------------------------------------- +checksums + +checksum 392 453 984 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 5b0d631..a5cf6c6 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -8,6 +8,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> @@ -22,6 +23,7 @@ #include <soc/soc_chip.h> #include <stdlib.h> #include <string.h> +#include <types.h>
/* THC assignment definition */ #define THC_NONE 0 @@ -489,8 +491,9 @@ const struct soc_intel_alderlake_config *config) { /* Legacy 8254 timer support */ - s_cfg->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + s_cfg->Enable8254ClockGating = !legacy_8254_timer; + s_cfg->Enable8254ClockGatingOnS3 = !legacy_8254_timer; }
static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 9d2d722..28ff0fc 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/power_limit.h> @@ -17,6 +18,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h> +#include <types.h>
#include "chip.h"
@@ -425,8 +427,9 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer;; + params->Enable8254ClockGatingOnS3 = !legacy_8254_timer;;
params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index 42613a8..e8d7207 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -3,16 +3,3 @@ help Intel Processor common TIMER support
-config USE_LEGACY_8254_TIMER - bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS || VGA_ROM_RUN - default n - help - Setting this makes the Legacy 8254 Timer available by disabling - clock gating. This needs to be enabled in order to boot a legacy - BIOS or OS not supporting other timers like PM timer or TSC. - - While SeaBIOS does not require this timer anymore, it is needed - when OpRoms are being used. - - Disable this setting to save power, when the timer is not needed. diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 210040e..a10f6e2 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -5,6 +5,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> #include <intelblocks/pmclib.h> @@ -15,6 +16,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <types.h>
/* SATA DEVSLP idle timeout default values */ #define DEF_DMVAL 15 @@ -142,7 +144,8 @@ params->PavpEnable = 0;
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer; params->Enable8254ClockGatingOnS3 = 1;
/* PCH Master Gating Control */ diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 2d63097..6301cc4 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -4,16 +4,18 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> +#include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> +#include <intelblocks/mp_init.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> -#include <intelblocks/mp_init.h> -#include <fsp/ppi/mp_service_ppi.h> +#include <types.h>
static void parse_devicetree(FSP_S_CONFIG *params) { @@ -93,8 +95,9 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer; + params->Enable8254ClockGatingOnS3 = !legacy_8254_timer;
/* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 45bed5e..d502ce3 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -5,6 +5,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> #include <intelblocks/pmclib.h> @@ -15,6 +16,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <types.h>
/* * ME End of Post configuration @@ -85,7 +87,8 @@ params->EndOfPostMessage = EOP_DISABLE;
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer;; params->Enable8254ClockGatingOnS3 = 1;
/* disable Legacy PME */ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 2599e12..51fcabd 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -18,6 +18,7 @@ #include <intelblocks/xdci.h> #include <intelblocks/p2sb.h> #include <intelpch/lockdown.h> +#include <option.h> #include <soc/acpi.h> #include <soc/intel/common/vbt.h> #include <soc/interrupt.h> @@ -29,6 +30,7 @@ #include <soc/systemagent.h> #include <soc/usb.h> #include <string.h> +#include <types.h>
#include "chip.h"
@@ -341,7 +343,8 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */ - params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Early8254ClockGatingEnable = !legacy_8254_timer;
params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index afbd747..a2b8dba 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -10,6 +10,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/cse.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> @@ -26,6 +27,7 @@ #include <soc/soc_chip.h> #include <soc/tcss.h> #include <string.h> +#include <types.h>
/* THC assignment definition */ #define THC_NONE 0 @@ -547,8 +549,9 @@ params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer; + params->Enable8254ClockGatingOnS3 = !legacy_8254_timer;
/* Enable Hybrid storage auto detection */ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()
-
Sean Rhodes (Code Review)