Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock - coreboot-gerrit

28 Jun 2019


      David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 )
Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
......................................................................
Patch Set 14: Code-Review+1
I tend to agree that spi probably does not belong in the function name.
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/25442
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Gerrit-Change-Number: 25442
Gerrit-PatchSet: 14
Gerrit-Owner: Julien Viard de Galbert coreboot-review-ju@vdg.name
Gerrit-Reviewer: David Guckian
Gerrit-Reviewer: David Guckian david.guckian@intel.com
Gerrit-Reviewer: Julien Viard de Galbert coreboot-review-ju@vdg.name
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Reviewer: Steve Mooney
Gerrit-Reviewer: Vanny E vanessa.f.eusebio@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Jay Talbott JayTalbott@sysproconsulting.com
Gerrit-CC: Lijian Zhao lijian.zhao@intel.com
Gerrit-Comment-Date: Fri, 28 Jun 2019 17:52:31 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment