Change in coreboot[master]: soc/intel/cnl: enable ACPI CPPC entries generation

[Michael Niewöhner (Code Review)]

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47541 )

Change subject: soc/intel/cnl: enable ACPI CPPC entries generation
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soc/intel/cnl: enable ACPI CPPC entries generation

Enable CPPC entries generation, needed for Intel SpeedShift.

Test: dumped SSDT from Clevo L140CU and checked decompiled version

Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47541
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 7b9b88b..f427340 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -103,6 +103,7 @@
    select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
    select SOC_INTEL_COMMON_BLOCK
    select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
    select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
    select SOC_INTEL_COMMON_BLOCK_CNVI
    select SOC_INTEL_COMMON_BLOCK_CPU