David Hendricks (dhendrix@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3319
-gerrit
commit ddf5f584c53d1373c3b094adf6923c712b13133f Author: David Hendricks dhendrix@chromium.org Date: Mon May 27 10:32:57 2013 -0700
am335x: struct for uart registers
This just adds a struct for referencing UART registers. The layout is quite strange on this chip, as the entire register space can take on three different meanings depending on the line control settings (in the LCR register). And to make things more confusing, some offsets reference different registers depending on if a read or a write operation is used.
Change-Id: Ie62af9c0e0edafd01b81686a0fe5c5c1d4fa06c4 Signed-off-by: David Hendricks dhendrix@chromium.org --- src/cpu/ti/am335x/uart.h | 90 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 87 insertions(+), 3 deletions(-)
diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index b642e9c..90e8779 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -23,8 +23,8 @@ * from u-boot. */
-#ifndef __AM335X_UART_H_ -#define __AM335X_UART_H +#ifndef AM335X_UART_H +#define AM335X_UART_H
#define AM335X_UART0_BASE 0x44e09000 #define AM335X_UART1_BASE 0x48020000 @@ -33,4 +33,88 @@ #define AM335X_UART4_BASE 0x481A8000 #define AM335X_UART5_BASE 0x481AA000
-#endif +struct am335x_uart { + union { + uint32_t rhr; /* receiver holding (read) */ + uint32_t thr; /* transmit holding (write) */ + }; + uint32_t ier; /* interrupt enable */ + union { + uint32_t iir; /* interrupt ID (read) */ + uint32_t fcr; /* FIFO control (write) */ + }; + uint32_t lcr; /* line control */ + + /* 0x10 */ + uint32_t mcr; /* modem control */ + uint32_t lsr; /* line status, read-only */ + + /* + * Bytes 0x18 and 0x1c are weird. When EFR[4] = 1 and MCR[6] = 1, + * transmission control register and trigger level register + * will be read/written. If not, the modem status register + * and scratchpad register will be affected by read/write. + */ + union { + uint32_t msr; /* modem status */ + uint32_t tcr; /* transmission control */ + }; + union { + uint32_t spr; /* scratchpad */ + uint32_t tlr; /* trigger level */ + }; + + /* 0x20 */ + uint32_t mdr1; /* mode definition 1 */ + uint32_t mdr2; /* mode definition 2 */ + union { + uint32_t sflsr; /* status FIFO line status reg (read) */ + uint32_t txfll; /* transmit frame length low (write) */ + }; + union { + uint32_t resume; /* resume halted operation (read) */ + uint32_t txflh; /* transmit frame length high (write) */ + }; + + /* 0x30 */ + union { + uint32_t sfregl; /* status FIFO low (read) */ + uint32_t rxfll; /* received frame length low (write) */ + }; + union { + uint32_t sfregh; /* status FIFO high (read) */ + uint32_t rxflh; /* received frame length high (write) */ + }; + uint32_t blr; /* BOF control */ + uint32_t acreg; /* auxilliary control */ + + /* 0x40 */ + uint32_t scr; /* supplementary control */ + uint32_t ssr; /* supplementary status */ + uint32_t eblr; /* BOF length */ + + /* 0x50 */ + uint32_t mvr; /* module version (read-only) */ + uint32_t sysc; /* system config */ + uint32_t syss; /* system status (read-only) */ + uint32_t wer; /* wake-up enable */ + + /* 0x60 */ + uint32_t cfps; /* carrier prescale frequency */ + uint32_t rxfifo_lvl; /* received FIFO level */ + uint32_t txfifo_lvl; /* transmit FIFO level */ + uint32_t ier2; + + /* 0x70 */ + uint32_t isr2; + uint32_t freq_sel; /* frequency select */ + uint32_t rsvd1; /* reserved */ + uint32_t rsvd2; /* reserved */ + + /* 0x80 */ + uint32_t mdr3; /* mode definition register 3 */ + uint32_t txdma; + +} __attribute__((packed)); + +#endif /* AM335X_UART_H */
-
David Hendricks