[S] Change in coreboot[main]: spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T

[Leo Chou (Code Review)]

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82782?usp=email )

Change subject: spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T
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spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T

This adds support for Zilia SDVB8D8A34XGCL3N3T LP4x chips.

Generatd SPD data with:
util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

BRANCH=None
BUG=344482259

Change-Id: I4408e62ab2a15002960c1d9659ab6af45bd7f7bb
Signed-off-by: Leo Chou 
---
M spd/lp4x/memory_parts.json
M spd/lp4x/set-0/parts_spd_manifest.generated.txt
M spd/lp4x/set-1/parts_spd_manifest.generated.txt
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/pujjoga/gpio.c
M src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h
6 files changed, 22 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82782/1

diff --git a/spd/lp4x/memory_parts.json b/spd/lp4x/memory_parts.json
index b0ec8b3..d4e0e9a 100644
--- a/spd/lp4x/memory_parts.json
+++ b/spd/lp4x/memory_parts.json
@@ -399,6 +399,18 @@
                 "ranksPerChannel": 1,
                 "speedMbps": 4267
             }
+	},
+	{
+            "name": "SDVB8D8A34XGCL3N3T",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
    }
     ]
 }
diff --git a/spd/lp4x/set-0/parts_spd_manifest.generated.txt b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
index f82c8bd..004d1bd 100644
--- a/spd/lp4x/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
@@ -34,3 +34,4 @@
 K4UCE3Q4AB-MGCL,spd-2.hex
 CXDB4ABAM-ML,spd-8.hex
 CXDB4CBAM-ML-A,spd-8.hex
+SDVB8D8A34XGCL3N3T,spd-1.hex
diff --git a/spd/lp4x/set-1/parts_spd_manifest.generated.txt b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
index 3a9201d..1604a11 100644
--- a/spd/lp4x/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
@@ -34,3 +34,4 @@
 K4UCE3Q4AB-MGCL,spd-2.hex
 CXDB4ABAM-ML,spd-11.hex
 CXDB4CBAM-ML-A,spd-11.hex
+SDVB8D8A34XGCL3N3T,spd-5.hex
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 366d2dd..b1330d2 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -418,6 +418,7 @@
 config BOARD_GOOGLE_PUJJOGA
    select BOARD_GOOGLE_BASEBOARD_NISSA
    select DRIVERS_GENERIC_GPIO_KEYS
+	select HAVE_WWAN_POWER_SEQUENCE

config BOARD_GOOGLE_QUANDISO
    select BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/variants/pujjoga/gpio.c b/src/mainboard/google/brya/variants/pujjoga/gpio.c
index cf5c9bd..880e3e3 100644
--- a/src/mainboard/google/brya/variants/pujjoga/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjoga/gpio.c
@@ -35,7 +35,7 @@
    /* E21  : NC */
    PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
    /* F12 : WWAN_RST_L */
-	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
+	PAD_CFG_GPO(GPP_F12, 1, DEEP),
    /* H12  : NC */
    PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
    /* H13  : NC */
@@ -89,6 +89,8 @@
    PAD_CFG_GPO(GPP_C0, 1, DEEP),
    /* C1  : SMBDATA ==> USI_RST_L */
    PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP),
+	/* F12 : WWAN_RST_L */
+	PAD_CFG_GPO(GPP_F12, 1, DEEP),
 };

const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h
index c4fe342..c96b01f 100644
--- a/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h
@@ -5,4 +5,8 @@

#include <baseboard/gpio.h>

+#define WWAN_FCPO	GPP_D6
+#define WWAN_RST	GPP_F12
+#define T2_OFF_MS	20
+
 #endif